From ee358ebecd27736007bbbc103f33da15d4ef5595 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Mon, 9 Dec 2019 08:50:53 +0100
Subject: [PATCH] low phase drift: add RX synchronizer
---
.../wr_gtx_phy_virtex6_lp.vhd | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd b/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
index d3762be4..9e881860 100644
--- a/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
+++ b/platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
@@ -251,6 +251,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_data_raw, rx_data_raw_d : std_logic_vector(19 downto 0);
+ signal rx_data_raw_gtx : std_logic_vector(19 downto 0);
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
@@ -482,7 +483,7 @@ begin -- rtl
-- RXBYTEISALIGNED_OUT => open,
-- RXCOMMADET_OUT => open,
-- RXSLIDE_IN => '0',
- RXDATA_OUT => rx_data_raw,
+ RXDATA_OUT => rx_data_raw_gtx,
RXRECCLK_OUT => rx_rec_clk_bufin,
RXUSRCLK2_IN => rx_rec_clk,
RXCDRRESET_IN => rx_cdr_reset_a,
@@ -514,6 +515,15 @@ begin -- rtl
TXPLLLKDET_OUT => txpll_lockdet,
TXRESETDONE_OUT => gtx_tx_rst_done);
+ RX_DAT_ANTI_META: gc_sync_register
+ generic map (
+ g_width => 20)
+ port map (
+ clk_i => rx_rec_clk,
+ rst_n_a_i => '1', --gtx_rst,
+ d_i => rx_data_raw_gtx,
+ q_o => rx_data_raw);
+
mgtrefclk_in <= '0' & clk_gtx_i;
rx_synced <= '0';
--
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