diff --git a/platform/xilinx/Manifest.py b/platform/xilinx/Manifest.py
index 79f7647b2af16eca4076369c79172bb21767bd7f..2747061f1740a278efbd4b95c914b2f65e525946 100644
--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
@@ -1,2 +1,2 @@
-files = [ "wr_xilinx_pkg.vhd", "ext_pll_10_to_125m.vhd", "xwrc_platform_xilinx.vhd" ]
-modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
+files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
+modules = {"local" : ["wr_gtp_phy", "chipscope"]}
diff --git a/platform/xilinx/ext_pll_10_to_125m.vhd b/platform/xilinx/ext_pll_10_to_125m.vhd
deleted file mode 100644
index 317f00558f133495817974999660a4832d5cebff..0000000000000000000000000000000000000000
--- a/platform/xilinx/ext_pll_10_to_125m.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
--- file: ext_pll_10_to_125m.vhd
---
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output Output Phase Duty Pk-to-Pk Phase"
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1___125.000______0.000______50.0_____1014.602____150.000
---
-------------------------------------------------------------------------------
--- "Input Clock Freq (MHz) Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary__________10.000____________0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity ext_pll_10_to_125m is
-port
- (-- Clock in ports
- clk_ext_i : in std_logic;
- -- Clock out ports
- clk_ext_mul_o : out std_logic;
- -- Status and control signals
- rst_a_i : in std_logic;
- clk_in_stopped_o : out std_logic;
- locked_o : out std_logic
- );
-end ext_pll_10_to_125m;
-
-architecture xilinx of ext_pll_10_to_125m is
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
- -- Input clock buffering / unused connectors
- signal clkin1 : std_logic;
- -- Output clock buffering
- signal clkfb : std_logic;
- signal clk0 : std_logic;
- signal clkfx : std_logic;
- signal clkfbout : std_logic;
- signal locked_internal : std_logic;
- signal status_internal : std_logic_vector(7 downto 0);
-begin
-
-
- -- Input buffering
- --------------------------------------
- clkin1 <= clk_ext_i;
-
-
- -- Clocking primitive
- --------------------------------------
-
- -- Instantiation of the DCM primitive
- -- * Unused inputs are tied off
- -- * Unused outputs are labeled unused
- dcm_sp_inst: DCM_SP
- generic map
- (CLKDV_DIVIDE => 2.000,
- CLKFX_DIVIDE => 2,
- CLKFX_MULTIPLY => 25,
- CLKIN_DIVIDE_BY_2 => FALSE,
- CLKIN_PERIOD => 100.0,
- CLKOUT_PHASE_SHIFT => "NONE",
- CLK_FEEDBACK => "1X",
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
- PHASE_SHIFT => 0,
- STARTUP_WAIT => FALSE)
- port map
- -- Input clock
- (CLKIN => clkin1,
- CLKFB => clkfb,
- -- Output clocks
- CLK0 => clk0,
- CLK90 => open,
- CLK180 => open,
- CLK270 => open,
- CLK2X => open,
- CLK2X180 => open,
- CLKFX => clkfx,
- CLKFX180 => open,
- CLKDV => open,
- -- Ports for dynamic phase shift
- PSCLK => '0',
- PSEN => '0',
- PSINCDEC => '0',
- PSDONE => open,
- -- Other control and status signals
- LOCKED => locked_internal,
- STATUS => status_internal,
- RST => rst_a_i,
- -- Unused pin, tie low
- DSSEN => '0');
-
- clk_in_stopped_o <= status_internal(1);
- locked_o <= locked_internal;
-
-
-
- -- Output buffering
- -------------------------------------
- clkf_buf : BUFG
- port map
- (O => clkfb,
- I => clk0);
-
-
- clkout1_buf : BUFG
- port map
- (O => clk_ext_mul_o,
- I => clkfx);
-
-
-
-end xilinx;
diff --git a/platform/xilinx/wr_xilinx_pkg.vhd b/platform/xilinx/wr_xilinx_pkg.vhd
index 5920d66c817b3ec490aa279ceabb0e5afd19cbfa..cb1953729ae0739ac0da5500f70e2d44d7796e0a 100644
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -2,93 +2,52 @@ library ieee;
use ieee.std_logic_1164.all;
library work;
-use work.genram_pkg.all;
-use work.wishbone_pkg.all;
-use work.sysc_wbgen2_pkg.all;
-use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
package wr_xilinx_pkg is
- -------------------------------------------------------------------------------------------
- -- records used as interface between WRPC and platform-specific module xwrc_platform_xilinx
- -------------------------------------------------------------------------------------------
- type t_sfp_from_wrc is record
- scl : std_logic;
- sda : std_logic;
- end record;
-
- type t_sfp_to_wrc is record
- scl : std_logic;
- sda : std_logic;
- det : std_logic;
- end record;
-
- type t_dacs_from_wrc is record
- hpll_load_p1 : std_logic;
- hpll_data : std_logic_vector(15 downto 0);
- dpll_load_p1 : std_logic;
- dpll_data : std_logic_vector(15 downto 0);
- end record;
-
- type t_extref_to_wrc is record
- clk_10m_ref : std_logic;
- clk_125m_ref : std_logic;
- locked : std_logic;
- stopped : std_logic;
- pps : std_logic;
- end record;
-
- -------------------------------------------------------------------------------------------
- component xwrc_platform_xilinx
- generic
- (
- g_simulation : integer := 0;
- g_family : string := "spartan6";
- g_with_10m_refin : integer := 0
- );
+ component xwrc_platform_xilinx is
+ generic (
+ g_fpga_family : string := "spartan6";
+ g_with_external_clock_input : boolean := FALSE;
+ g_use_default_plls : boolean := TRUE;
+ g_simulation : integer := 0);
port (
- local_reset_n_i : in std_logic;
- clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
- clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
- clk_125m_pllref_n_i : in std_logic;
- clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
- clk_125m_gtp_p_i : in std_logic; -- 125 MHz GTP reference
- clk_10m_ref_p_i : in std_logic := '0'; -- 10MHz external reference
- clk_10m_ref_n_i : in std_logic := '0'; -- 10MHz external reference
- pps_ext_i : in std_logic := '0'; -- external 1-PPS from reference
- dac_sclk_o : out std_logic; -- Serial Clock Line
- dac_din_o : out std_logic; -- Serial Data Line
- dac_cs1_n_o : out std_logic; -- Chip Select
- dac_cs2_n_o : out std_logic; -- Chip Select
- carrier_onewire_b : inout std_logic := '1'; -- read temperature sensor
- sfp_txp_o : out std_logic;
- sfp_txn_o : out std_logic;
- sfp_rxp_i : in std_logic;
- sfp_rxn_i : in std_logic;
- sfp_mod_def0_i : in std_logic; -- sfp detect
- sfp_mod_def1_b : inout std_logic; -- Config-I2C: Clk Line
- sfp_mod_def2_b : inout std_logic; -- Config-I2C: Data Line
- sfp_rate_select_b : inout std_logic;
- sfp_tx_fault_i : in std_logic;
- sfp_tx_disable_o : out std_logic;
- sfp_los_i : in std_logic;
- clk_62m5_sys_o : out std_logic;
- clk_125m_pllref_o : out std_logic;
- clk_62m5_dmtd_o : out std_logic;
- dacs_i : in t_dacs_from_wrc;
- phy8_o : out t_phy_8bits_to_wrc;
- phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
- phy16_o : out t_phy_16bits_to_wrc;
- phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
- owr_en_i : in std_logic_vector(1 downto 0);
- owr_o : out std_logic_vector(1 downto 0);
- sfp_config_o : out t_sfp_to_wrc;
- sfp_config_i : in t_sfp_from_wrc;
- ext_ref_o : out t_extref_to_wrc;
- ext_ref_rst_i : in std_logic := '0'
- );
- end component;
+ areset_n_i : in std_logic := '1';
+ clk_10m_ext_i : in std_logic := '0';
+ clk_125m_gtp_p_i : in std_logic;
+ clk_125m_gtp_n_i : in std_logic;
+ clk_20m_vcxo_i : in std_logic := '0';
+ clk_125m_pllref_i : in std_logic := '0';
+ clk_62m5_dmtd_i : in std_logic := '0';
+ clk_dmtd_locked_i : in std_logic := '1';
+ clk_62m5_sys_i : in std_logic := '0';
+ clk_sys_locked_i : in std_logic := '1';
+ clk_125m_ref_i : in std_logic := '0';
+ clk_125m_ext_i : in std_logic := '0';
+ clk_ext_locked_i : in std_logic := '1';
+ clk_ext_stopped_i : in std_logic := '0';
+ clk_ext_rst_o : out std_logic;
+ sfp_txn_o : out std_logic;
+ sfp_txp_o : out std_logic;
+ sfp_rxn_i : in std_logic;
+ sfp_rxp_i : in std_logic;
+ sfp_tx_fault_i : in std_logic := '0';
+ sfp_los_i : in std_logic := '0';
+ sfp_tx_disable_o : out std_logic;
+ clk_62m5_sys_o : out std_logic;
+ clk_125m_ref_o : out std_logic;
+ clk_62m5_dmtd_o : out std_logic;
+ pll_locked_o : out std_logic;
+ phy8_o : out t_phy_8bits_to_wrc;
+ phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
+ phy16_o : out t_phy_16bits_to_wrc;
+ phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+ ext_ref_mul_o : out std_logic;
+ ext_ref_mul_locked_o : out std_logic;
+ ext_ref_mul_stopped_o : out std_logic;
+ ext_ref_rst_i : in std_logic := '0');
+ end component xwrc_platform_xilinx;
component wr_gtp_phy_spartan6
generic (
@@ -97,7 +56,7 @@ package wr_xilinx_pkg is
g_simulation : integer := 0);
port (
gtp_clk_i : in std_logic;
- ch0_ref_clk_i : in std_logic := '0';
+ ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
@@ -107,10 +66,10 @@ package wr_xilinx_pkg is
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
- ch0_rst_i : in std_logic := '0';
- ch0_loopen_i : in std_logic := '0';
- ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
- ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
+ ch0_rst_i : in std_logic := '0';
+ ch0_loopen_i : in std_logic := '0';
+ ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
+ ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_rdy_o : out std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
@@ -124,8 +83,8 @@ package wr_xilinx_pkg is
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
- ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
- ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
+ ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
+ ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
@@ -162,13 +121,4 @@ package wr_xilinx_pkg is
pad_rxp_i : in std_logic := '0');
end component;
- component ext_pll_10_to_125m
- port (
- clk_ext_i : in std_logic;
- clk_ext_mul_o : out std_logic;
- rst_a_i : in std_logic;
- clk_in_stopped_o: out std_logic;
- locked_o : out std_logic);
- end component ext_pll_10_to_125m;
-
end wr_xilinx_pkg;
diff --git a/platform/xilinx/xwrc_platform_xilinx.vhd b/platform/xilinx/xwrc_platform_xilinx.vhd
index 428192183595261bd41d13d64b1cbbd506f0e075..8d48884813893320bec11dd7a63719d7b658a04e 100644
--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -1,9 +1,10 @@
-------------------------------------------------------------------------------
-- Title : Platform-dependent components needed for WR PTP Core on Xilinx
-- Project : WR PTP Core
+-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wrc_platform_xilinx.vhd
--- Author : Maciej Lipinski, Grzegorz Daniluk
+-- Author : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
-- Company : CERN
-- Platform : FPGA-generic
-- Standard : VHDL'93
@@ -15,12 +16,10 @@
-- * PHY
-- * PLLs
-- * buffers
--- * controller of DACs
--- * access to SFP config
--
-------------------------------------------------------------------------------
--
--- Copyright (c) 2016 CERN / BE-CO-HT
+-- Copyright (c) 2016-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
@@ -40,376 +39,393 @@
--
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
+library ieee;
+use ieee.std_logic_1164.all;
-use work.wr_fabric_pkg.all;
-use work.wishbone_pkg.all;
-use work.wr_xilinx_pkg.all;
-use work.wrcore_pkg.all;
-use work.gencores_pkg.all;
+library work;
use work.endpoint_pkg.all;
+use work.gencores_pkg.all;
+use work.wr_xilinx_pkg.all;
-library UNISIM;
-use UNISIM.vcomponents.all;
+library unisim;
+use unisim.vcomponents.all;
entity xwrc_platform_xilinx is
generic
(
- -- setting g_simulation to TRUE will speed up some initialization processes
- g_simulation : integer := 0;
- -- define the Familiy of Xilinx FPGAs (supported: now only spartan6)
- g_family : string := "spartan6";
- g_with_10m_refin : integer := 0
- );
- port (
- local_reset_n_i : in std_logic;
- ---------------------------------------------------------------------------------------
- -- main clocks
- ---------------------------------------------------------------------------------------
- clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
- clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
- clk_125m_pllref_n_i : in std_logic;
- clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
- clk_125m_gtp_p_i : in std_logic; -- 125 MHz GTP reference
-
- ---------------------------------------------------------------------------------------
- -- External 10MHz & 1-PPS reference
- ---------------------------------------------------------------------------------------
- clk_10m_ref_p_i : in std_logic := '0'; -- 10MHz external reference
- clk_10m_ref_n_i : in std_logic := '0'; -- 10MHz external reference
- pps_ext_i : in std_logic := '0'; -- external 1-PPS from reference
-
- ---------------------------------------------------------------------------------------
- -- I2C to control DAC
- ---------------------------------------------------------------------------------------
- dac_sclk_o : out std_logic; -- Serial Clock Line
- dac_din_o : out std_logic; -- Serial Data Line
- dac_cs1_n_o : out std_logic; -- Chip Select
- dac_cs2_n_o : out std_logic; -- Chip Select
-
- ---------------------------------------------------------------------------------------
- -- one-wire access to thermometer
- ---------------------------------------------------------------------------------------
- carrier_onewire_b : inout std_logic := '1'; -- read temperature sensor
-
- ---------------------------------------------------------------------------------------
- -- SFP pins
- ---------------------------------------------------------------------------------------
- sfp_txp_o : out std_logic;
- sfp_txn_o : out std_logic;
- sfp_rxp_i : in std_logic;
- sfp_rxn_i : in std_logic;
- sfp_mod_def0_i : in std_logic; -- sfp detect
- sfp_mod_def1_b : inout std_logic; -- Config-I2C: Clk Line
- sfp_mod_def2_b : inout std_logic; -- Config-I2C: Data Line
- sfp_rate_select_b : inout std_logic;
- sfp_tx_fault_i : in std_logic;
- sfp_tx_disable_o : out std_logic;
- sfp_los_i : in std_logic;
-
- ---------------------------------------------------------------------------------------
- --Interface to WR PTP Core (WRPC)
- ---------------------------------------------------------------------------------------
-
- clk_62m5_sys_o : out std_logic;
- clk_125m_pllref_o : out std_logic;
- clk_62m5_dmtd_o : out std_logic;
- dacs_i : in t_dacs_from_wrc;
- phy8_o : out t_phy_8bits_to_wrc;
- phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
- phy16_o : out t_phy_16bits_to_wrc;
- phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
- owr_en_i : in std_logic_vector(1 downto 0);
- owr_o : out std_logic_vector(1 downto 0);
- sfp_config_o : out t_sfp_to_wrc;
- sfp_config_i : in t_sfp_from_wrc;
- ext_ref_o : out t_extref_to_wrc;
- ext_ref_rst_i : in std_logic := '0'
+ -- Define the family/model of Xilinx FPGA
+ -- (supported: for now only spartan6)
+ g_fpga_family : string := "spartan6";
+ -- Select whether to include external ref clock input
+ g_with_external_clock_input : boolean := FALSE;
+ -- Set to FALSE if you want to instantiate your own PLLs
+ g_use_default_plls : boolean := TRUE;
+ -- Set to TRUE will speed up some initialization processes
+ g_simulation : integer := 0
);
+ port (
+ ---------------------------------------------------------------------------
+ -- Asynchronous reset (active low)
+ ---------------------------------------------------------------------------
+ areset_n_i : in std_logic;
+ ---------------------------------------------------------------------------
+ -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
+ ---------------------------------------------------------------------------
+ clk_10m_ext_i : in std_logic := '0';
+ ---------------------------------------------------------------------------
+ -- 125 MHz GTP reference
+ ---------------------------------------------------------------------------
+ clk_125m_gtp_p_i : in std_logic;
+ clk_125m_gtp_n_i : in std_logic;
+ ---------------------------------------------------------------------------
+ -- Clock inputs for default PLLs (g_use_default_plls = TRUE)
+ ---------------------------------------------------------------------------
+ -- 20MHz VCXO clock
+ clk_20m_vcxo_i : in std_logic := '0';
+ -- 125 MHz PLL reference
+ clk_125m_pllref_i : in std_logic := '0';
+ ---------------------------------------------------------------------------
+ -- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
+ ---------------------------------------------------------------------------
+ -- 62.5MHz DMTD offset clock and lock status
+ clk_62m5_dmtd_i : in std_logic := '0';
+ clk_dmtd_locked_i : in std_logic := '1';
+ -- 62.5MHz Main system clock and lock status
+ clk_62m5_sys_i : in std_logic := '0';
+ clk_sys_locked_i : in std_logic := '1';
+ -- 125MHz Reference clock
+ clk_125m_ref_i : in std_logic := '0';
+ -- 125MHz derived from 10MHz external reference and lock status
+ -- (when g_with_external_clock_input = TRUE)
+ clk_125m_ext_i : in std_logic := '0';
+ clk_ext_locked_i : in std_logic := '1';
+ clk_ext_stopped_i : in std_logic := '0';
+ clk_ext_rst_o : out std_logic;
+ ---------------------------------------------------------------------------
+ -- SFP
+ ---------------------------------------------------------------------------
+ sfp_txn_o : out std_logic;
+ sfp_txp_o : out std_logic;
+ sfp_rxn_i : in std_logic;
+ sfp_rxp_i : in std_logic;
+ sfp_tx_fault_i : in std_logic := '0';
+ sfp_los_i : in std_logic := '0';
+ sfp_tx_disable_o : out std_logic;
+ ---------------------------------------------------------------------------
+ --Interface to WR PTP Core (WRPC)
+ ---------------------------------------------------------------------------
+ -- PLL outputs
+ clk_62m5_sys_o : out std_logic;
+ clk_125m_ref_o : out std_logic;
+ clk_62m5_dmtd_o : out std_logic;
+ pll_locked_o : out std_logic;
+ -- PHY
+ phy8_o : out t_phy_8bits_to_wrc;
+ phy8_i : in t_phy_8bits_from_wrc := c_dummy_phy8_from_wrc;
+ phy16_o : out t_phy_16bits_to_wrc;
+ phy16_i : in t_phy_16bits_from_wrc := c_dummy_phy16_from_wrc;
+ -- External reference
+ ext_ref_mul_o : out std_logic;
+ ext_ref_mul_locked_o : out std_logic;
+ ext_ref_mul_stopped_o : out std_logic;
+ ext_ref_rst_i : in std_logic := '0'
+ );
-end xwrc_platform_xilinx;
+end entity xwrc_platform_xilinx;
architecture rtl of xwrc_platform_xilinx is
-------------------------------------------------------------------------------------------
-- Signals declaration
-------------------------------------------------------------------------------------------
- -- Clocks
- signal clk_62m5_pllout_sys : std_logic;
- signal clk_62m5_pllout_dmtd : std_logic;
- signal clk_62m5_pllout_fb_pllref : std_logic;
- signal clk_62m5_pllout_fb_dmtd : std_logic;
- signal clk_20m_vcxo_buf : std_logic;
- signal clk_125m_pllref : std_logic;
- signal clk_125m_pllref_bufg : std_logic;
- signal clk_125m_gtp : std_logic;
- signal clk_62m5_sys : std_logic;
- signal clk_80m_ADC : std_logic;
-
- -- External 10MHz reference
- signal clk_10m_ref : std_logic;
- signal clk_10m_ref_bufg : std_logic;
- signal ext_pll_rst : std_logic;
-
- -- WRPC <--> EEPROM on FMC
- signal wrc_scl_out : std_logic;
- signal wrc_sda_out : std_logic;
- signal wrc_scl_in : std_logic;
- signal wrc_sda_in : std_logic;
-
- -- WRPC <--> SFP config
- signal sfp_scl_out : std_logic;
- signal sfp_scl_in : std_logic;
- signal sfp_sda_out : std_logic;
- signal sfp_sda_in : std_logic;
-
-begin
-
- -------------------------------------------------------------------------------------------
- -- all the clock-related stuff (PLLs etc)
- -------------------------------------------------------------------------------------------
- cmp_sys_clk_pll : PLL_BASE
- generic map (
- BANDWIDTH => "OPTIMIZED",
- CLK_FEEDBACK => "CLKFBOUT",
- COMPENSATION => "INTERNAL",
- DIVCLK_DIVIDE => 1,
- CLKFBOUT_MULT => 8,
- CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
- CLKOUT0_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 16, -- 62.5 MHz
- CLKOUT1_PHASE => 0.000,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DIVIDE => 16,
- CLKOUT2_PHASE => 0.000,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKIN_PERIOD => 8.0,
- REF_JITTER => 0.016)
- port map (
- CLKFBOUT => clk_62m5_pllout_fb_pllref,
- CLKOUT0 => clk_62m5_pllout_sys,
- CLKOUT1 => open,
- CLKOUT2 => open,
- CLKOUT3 => open,
- CLKOUT4 => open,
- CLKOUT5 => open,
- LOCKED => open,
- RST => '0',
- CLKFBIN => clk_62m5_pllout_fb_pllref,
- CLKIN => clk_125m_pllref_bufg);
-
- cmp_dmtd_clk_pll : PLL_BASE
- generic map (
- BANDWIDTH => "OPTIMIZED",
- CLK_FEEDBACK => "CLKFBOUT",
- COMPENSATION => "INTERNAL",
- DIVCLK_DIVIDE => 1,
- CLKFBOUT_MULT => 50,
- CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
- CLKOUT0_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 16, -- 62.5 MHz
- CLKOUT1_PHASE => 0.000,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DIVIDE => 8,
- CLKOUT2_PHASE => 0.000,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKIN_PERIOD => 50.0,
- REF_JITTER => 0.016)
- port map (
- CLKFBOUT => clk_62m5_pllout_fb_dmtd,
- CLKOUT0 => clk_62m5_pllout_dmtd,
- CLKOUT1 => open,
- CLKOUT2 => open,
- CLKOUT3 => open,
- CLKOUT4 => open,
- CLKOUT5 => open,
- LOCKED => open,
- RST => '0',
- CLKFBIN => clk_62m5_pllout_fb_dmtd,
- CLKIN => clk_20m_vcxo_buf);
-
- cmp_clk_sys_buf : BUFG
- port map (
- O => clk_62m5_sys,
- I => clk_62m5_pllout_sys);
-
- clk_62m5_sys_o <= clk_62m5_sys;
-
- cmp_clk_dmtd_buf : BUFG
- port map (
- O => clk_62m5_dmtd_o,
- I => clk_62m5_pllout_dmtd);
-
- cmp_clk_vcxo : BUFG
- port map (
- O => clk_20m_vcxo_buf,
- I => clk_20m_vcxo_i );
-
- cmp_pllrefclk_buf : IBUFGDS
- generic map (
- DIFF_TERM => true, -- Differential Termination
- IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE)
- -- setting for referenced I/O standards
- IOSTANDARD => "DEFAULT")
- port map (
- O => clk_125m_pllref, -- Buffer output
- I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly
- -- to top-level port)
- IB => clk_125m_pllref_n_i );-- Diff_n buffer input (connect directly
- -- to top-level port)
- cmp_pllrefclk_bufg : BUFG
- port map (
- O => clk_125m_pllref_bufg,
- I => clk_125m_pllref);
-
- phy8_o.ref_clk <= clk_125m_pllref_bufg;
- clk_125m_pllref_o <= clk_125m_pllref_bufg;
-
- -------------------------------------------------------------------------------------------
- -- Dedicated clock for GTP --ML: different in SPEC -> need check
- -------------------------------------------------------------------------------------------
- cmp_Dedicated_GTP_Clock_Buffer : IBUFGDS
- generic map(
- DIFF_TERM => true,
- IBUF_LOW_PWR => true,
- IOSTANDARD => "DEFAULT")
- port map (
- O => clk_125m_gtp,
- I => clk_125m_gtp_p_i,
- IB => clk_125m_gtp_n_i
- );
- -------------------------------------------------------------------------------------------
- -- PLL for multiplying external 10MHz reference clock
- -------------------------------------------------------------------------------------------
- GEN_EXT_REF: if g_with_10m_refin = 1 generate
- U_Ext_BUF : IBUFGDS
+ signal pll_arst : std_logic := '0';
+ signal clk_125m_pllref_buf : std_logic;
+
+begin -- architecture rtl
+
+ -----------------------------------------------------------------------------
+ -- Check for unsupported features and/or misconfiguration
+ -----------------------------------------------------------------------------
+ gen_unknown_fpga : if (g_fpga_family /= "spartan6") generate
+ assert FALSE
+ report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
+ severity ERROR;
+ end generate gen_unknown_fpga;
+
+ -----------------------------------------------------------------------------
+ -- Clock PLLs
+ -----------------------------------------------------------------------------
+
+ -- active high async reset for PLLs
+ pll_arst <= not areset_n_i;
+
+ gen_default_plls : if (g_use_default_plls = TRUE) generate
+
+ -- Default PLL setup consists of two PLLs.
+ -- One takes a 125MHz clock signal as input and produces the
+ -- 62.5MHz WR PTP core main system clock.
+ -- The other PLL takes a 20MHz clock signal as input and produces the
+ -- 62.5MHz DMTD clock.
+ --
+ -- A third PLL is instantiated if also g_with_external_clock_input = TRUE.
+ -- In that case, a 10MHz external reference is multiplied to generate a
+ -- 125MHz reference clock
+ gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
+
+ signal clk_sys : std_logic;
+ signal clk_sys_out : std_logic;
+ signal clk_sys_fb : std_logic;
+ signal pll_sys_locked : std_logic;
+ signal clk_dmtd : std_logic;
+ signal clk_dmtd_fb : std_logic;
+ signal pll_dmtd_locked : std_logic;
+ signal clk_20m_vcxo_buf : std_logic;
+
+ begin --gen_spartan6_default_plls
+
+ -- System PLL
+ cmp_sys_clk_pll : PLL_BASE
+ generic map (
+ BANDWIDTH => "OPTIMIZED",
+ CLK_FEEDBACK => "CLKFBOUT",
+ COMPENSATION => "INTERNAL",
+ DIVCLK_DIVIDE => 1,
+ CLKFBOUT_MULT => 8,
+ CLKFBOUT_PHASE => 0.000,
+ CLKOUT0_DIVIDE => 16,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKIN_PERIOD => 8.0,
+ REF_JITTER => 0.016)
+ port map (
+ CLKFBOUT => clk_sys_fb,
+ CLKOUT0 => clk_sys,
+ LOCKED => pll_sys_locked,
+ RST => pll_arst,
+ CLKFBIN => clk_sys_fb,
+ CLKIN => clk_125m_pllref_buf);
+
+ -- System PLL input clock buffer
+ cmp_clk_sys_buf_i : BUFG
+ port map (
+ O => clk_125m_pllref_buf,
+ I => clk_125m_pllref_i);
+
+ -- System PLL output clock buffer
+ cmp_clk_sys_buf_o : BUFG
+ port map (
+ O => clk_sys_out,
+ I => clk_sys);
+
+ clk_62m5_sys_o <= clk_sys_out;
+ clk_125m_ref_o <= clk_125m_pllref_buf;
+ pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
+
+ -- DMTD PLL
+ cmp_dmtd_clk_pll : PLL_BASE
+ generic map (
+ BANDWIDTH => "OPTIMIZED",
+ CLK_FEEDBACK => "CLKFBOUT",
+ COMPENSATION => "INTERNAL",
+ DIVCLK_DIVIDE => 1,
+ CLKFBOUT_MULT => 50,
+ CLKFBOUT_PHASE => 0.000,
+ CLKOUT0_DIVIDE => 16,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKIN_PERIOD => 50.0,
+ REF_JITTER => 0.016)
+ port map (
+ CLKFBOUT => clk_dmtd_fb,
+ CLKOUT0 => clk_dmtd,
+ LOCKED => pll_dmtd_locked,
+ RST => pll_arst,
+ CLKFBIN => clk_dmtd_fb,
+ CLKIN => clk_20m_vcxo_buf);
+
+ -- DMTD PLL input clock buffer
+ cmp_clk_dmtd_buf_i : BUFG
+ port map (
+ O => clk_20m_vcxo_buf,
+ I => clk_20m_vcxo_i);
+
+ -- DMTD PLL output clock buffer
+ cmp_clk_dmtd_buf_o : BUFG
+ port map (
+ O => clk_62m5_dmtd_o,
+ I => clk_dmtd);
+
+
+ gen_spartan6_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
+
+ signal clk_ext_fbi : std_logic;
+ signal clk_ext_fbo : std_logic;
+ signal clk_ext_in : std_logic;
+ signal clk_ext : std_logic;
+ signal clk_ext_stat : std_logic_vector(7 downto 0);
+ signal pll_ext_rst : std_logic;
+
+ begin --gen_spartan6_ext_ref_pll
+
+ -- External reference DCM
+ cmp_ext_ref_pll : DCM_SP
+ generic map
+ (CLKDV_DIVIDE => 2.000,
+ CLKFX_DIVIDE => 2,
+ CLKFX_MULTIPLY => 25,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 100.0,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ CLK_FEEDBACK => "1X",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map
+ -- Input clock
+ (CLKIN => clk_ext_in,
+ CLKFB => clk_ext_fbi,
+ -- Output clocks
+ CLK0 => clk_ext_fbo,
+ CLKFX => clk_ext,
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => open,
+ -- Other control and status signals
+ LOCKED => ext_ref_mul_locked_o,
+ STATUS => clk_ext_stat,
+ RST => pll_ext_rst,
+ -- Unused pin, tie low
+ DSSEN => '0');
+
+ ext_ref_mul_stopped_o <= clk_ext_stat(1);
+
+ -- External reference input buffer
+ cmp_clk_ext_buf_i : BUFG
+ port map
+ (O => clk_ext_in,
+ I => clk_10m_ext_i);
+
+ -- External reference feedback buffer
+ cmp_clk_ext_buf_fb : BUFG
+ port map
+ (O => clk_ext_fbi,
+ I => clk_ext_fbo);
+
+ -- External reference output buffer
+ cmp_clk_ext_buf_o : BUFG
+ port map
+ (O => ext_ref_mul_o,
+ I => clk_ext);
+
+ cmp_extend_ext_reset : gc_extend_pulse
+ generic map (
+ g_width => 1000)
+ port map (
+ clk_i => clk_sys_out,
+ rst_n_i => pll_sys_locked,
+ pulse_i => ext_ref_rst_i,
+ extended_o => pll_ext_rst);
+
+ end generate gen_spartan6_ext_ref_pll;
+
+ end generate gen_spartan6_default_plls;
+
+ end generate gen_default_plls;
+
+ -- If external PLLs are used, just copy clock inputs to outputs
+ gen_custom_plls : if (g_use_default_plls = FALSE) generate
+
+ clk_62m5_sys_o <= clk_62m5_sys_i;
+ clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
+ clk_125m_ref_o <= clk_125m_ref_i;
+
+ pll_locked_o <= clk_sys_locked_i and clk_dmtd_locked_i;
+
+ ext_ref_mul_o <= clk_125m_ext_i;
+ ext_ref_mul_locked_o <= clk_ext_locked_i;
+ ext_ref_mul_stopped_o <= clk_ext_stopped_i;
+
+ end generate gen_custom_plls;
+
+ -- always pass ext reference reset input to output, even when not used
+ clk_ext_rst_o <= ext_ref_rst_i;
+
+ -----------------------------------------------------------------------------
+ -- Transceiver PHY
+ -----------------------------------------------------------------------------
+
+ gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
+
+ signal clk_125m_gtp_buf : std_logic;
+
+ begin
+
+ cmp_ibufgds_gtp : IBUFGDS
generic map (
- DIFF_TERM => true)
+ DIFF_TERM => TRUE,
+ IBUF_LOW_PWR => TRUE,
+ IOSTANDARD => "DEFAULT")
port map (
- O => clk_10m_ref,
- I => clk_10m_ref_p_i,
- IB => clk_10m_ref_n_i);
+ O => clk_125m_gtp_buf,
+ I => clk_125m_gtp_p_i,
+ IB => clk_125m_gtp_n_i);
- U_Ext_BUFG : BUFG
- port map (
- O => clk_10m_ref_bufg,
- I => clk_10m_ref);
-
- U_Ext_PLL : ext_pll_10_to_125m
- port map (
- clk_ext_i => clk_10m_ref_bufg,
- clk_ext_mul_o => ext_ref_o.clk_125m_ref,
- rst_a_i => ext_pll_rst,
- clk_in_stopped_o => ext_ref_o.stopped,
- locked_o => ext_ref_o.locked);
- U_Extend_EXT_Reset : gc_extend_pulse
+ cmp_gtp : wr_gtp_phy_spartan6
generic map (
- g_width => 1000)
+ g_simulation => g_simulation,
+ g_enable_ch0 => 0,
+ g_enable_ch1 => 1)
port map (
- clk_i => clk_62m5_sys,
- rst_n_i => local_reset_n_i,
- pulse_i => ext_ref_rst_i,
- extended_o => ext_pll_rst);
- end generate;
- ext_ref_o.clk_10m_ref <= clk_10m_ref_bufg;
- ext_ref_o.pps <= pps_ext_i;
-
- -------------------------------------------------------------------------------
- -- Tri-state access to devices (SFP, one wire thermometer)
- -------------------------------------------------------------------------------
-
- -- Tristates for SFP EEPROM
- sfp_mod_def1_b <= '0' when sfp_config_i.scl = '0' else 'Z';
- sfp_mod_def2_b <= '0' when sfp_config_i.sda = '0' else 'Z';
- sfp_config_o.scl <= sfp_mod_def1_b;
- sfp_config_o.sda <= sfp_mod_def2_b;
-
- sfp_config_o.det <= sfp_mod_def0_i;
-
- carrier_onewire_b <= '0' when owr_en_i(0) = '1' else 'Z';
- owr_o(0) <= carrier_onewire_b;
-
- -------------------------------------------------------------------------------
- -- PHY
- -------------------------------------------------------------------------------
- gen_phy_spartan6: if(g_family = "spartan6") generate
- cmp_GTP : wr_gtp_phy_spartan6
- generic map (
- g_simulation => g_simulation,
- g_enable_ch0 => 0,
- g_enable_ch1 => 1)
- port map (
- gtp_clk_i => clk_125m_gtp,
- ch0_ref_clk_i => clk_125m_pllref_bufg,
- ch0_tx_data_i => x"00",
- ch0_tx_k_i => '0',
- ch0_tx_disparity_o => open,
- ch0_tx_enc_err_o => open,
- ch0_rx_rbclk_o => open,
- ch0_rx_data_o => open,
- ch0_rx_k_o => open,
- ch0_rx_enc_err_o => open,
- ch0_rx_bitslide_o => open,
- ch0_rst_i => '1',
- ch0_loopen_i => '0',
- ch1_ref_clk_i => clk_125m_pllref_bufg,
- ch1_tx_data_i => phy8_i.tx_data,
- ch1_tx_k_i => phy8_i.tx_k(0),
- ch1_tx_disparity_o => phy8_o.tx_disparity,
- ch1_tx_enc_err_o => phy8_o.tx_enc_err,
- ch1_rx_data_o => phy8_o.rx_data,
- ch1_rx_rbclk_o => phy8_o.rx_clk,
- ch1_rx_k_o => phy8_o.rx_k(0),
- ch1_rx_enc_err_o => phy8_o.rx_enc_err,
- ch1_rx_bitslide_o => phy8_o.rx_bitslide,
- ch1_rst_i => phy8_i.rst,
- ch1_loopen_i => phy8_i.loopen,
- ch1_loopen_vec_i => phy8_i.loopen_vec,
- ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
- ch1_rdy_o => phy8_o.rdy,
- pad_txn0_o => open,
- pad_txp0_o => open,
- pad_rxn0_i => '0',
- pad_rxp0_i => '0',
- pad_txn1_o => sfp_txn_o,
- pad_txp1_o => sfp_txp_o,
- pad_rxn1_i => sfp_rxn_i,
- pad_rxp1_i => sfp_rxp_i
- );
- sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
+ gtp_clk_i => clk_125m_gtp_buf,
+ ch0_ref_clk_i => clk_125m_pllref_buf,
+ ch0_tx_data_i => x"00",
+ ch0_tx_k_i => '0',
+ ch0_tx_disparity_o => open,
+ ch0_tx_enc_err_o => open,
+ ch0_rx_rbclk_o => open,
+ ch0_rx_data_o => open,
+ ch0_rx_k_o => open,
+ ch0_rx_enc_err_o => open,
+ ch0_rx_bitslide_o => open,
+ ch0_rst_i => '1',
+ ch0_loopen_i => '0',
+ ch1_ref_clk_i => clk_125m_pllref_buf,
+ ch1_tx_data_i => phy8_i.tx_data,
+ ch1_tx_k_i => phy8_i.tx_k(0),
+ ch1_tx_disparity_o => phy8_o.tx_disparity,
+ ch1_tx_enc_err_o => phy8_o.tx_enc_err,
+ ch1_rx_data_o => phy8_o.rx_data,
+ ch1_rx_rbclk_o => phy8_o.rx_clk,
+ ch1_rx_k_o => phy8_o.rx_k(0),
+ ch1_rx_enc_err_o => phy8_o.rx_enc_err,
+ ch1_rx_bitslide_o => phy8_o.rx_bitslide,
+ ch1_rst_i => phy8_i.rst,
+ ch1_loopen_i => phy8_i.loopen,
+ ch1_loopen_vec_i => phy8_i.loopen_vec,
+ ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
+ ch1_rdy_o => phy8_o.rdy,
+ pad_txn0_o => open,
+ pad_txp0_o => open,
+ pad_rxn0_i => '0',
+ pad_rxp0_i => '0',
+ pad_txn1_o => sfp_txn_o,
+ pad_txp1_o => sfp_txp_o,
+ pad_rxn1_i => sfp_rxn_i,
+ pad_rxp1_i => sfp_rxp_i
+ );
+
+ phy8_o.ref_clk <= clk_125m_pllref_buf;
phy8_o.sfp_tx_fault <= sfp_tx_fault_i;
phy8_o.sfp_los <= sfp_los_i;
+
+ sfp_tx_disable_o <= phy8_i.sfp_tx_disable;
+
+ phy16_o <= c_dummy_phy16_to_wrc;
+
end generate gen_phy_spartan6;
- gen_phy_unknown: if(g_family /= "spartan6") generate
- assert false report "unknown family for Xilinx is specified" severity error;
- end generate gen_phy_unknown;
-
- -------------------------------------------------------------------------------
- -- DAC control
- -------------------------------------------------------------------------------
- cmp_DAC_ARB : spec_serial_dac_arb
- generic map (
- g_invert_sclk => false,
- g_num_extra_bits => 8)
- port map (
- clk_i => clk_62m5_sys,
- rst_n_i => local_reset_n_i,
- val1_i => dacs_i.dpll_data,
- load1_i => dacs_i.dpll_load_p1,
- val2_i => dacs_i.hpll_data,
- load2_i => dacs_i.hpll_load_p1,
- dac_cs_n_o(0) => dac_cs1_n_o,
- dac_cs_n_o(1) => dac_cs2_n_o,
- dac_sclk_o => dac_sclk_o,
- dac_din_o => dac_din_o);
-
-end rtl;
+end architecture rtl;