diff --git a/modules/wr_endpoint/endpoint_private_pkg.vhd b/modules/wr_endpoint/endpoint_private_pkg.vhd
index 42a76bf0a1475c6d6e87186744fb0b9c8489a1f2..5bb058cd773a2fb897aed65b3c246da3ff6e3a08 100644
--- a/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_private_pkg.vhd
@@ -45,6 +45,7 @@ use ieee.numeric_std.all;
use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
+use work.genram_pkg.all;
package endpoint_private_pkg is
@@ -113,59 +114,226 @@ package endpoint_private_pkg is
end record;
component ep_1000basex_pcs
+ generic (
+ g_simulation : boolean;
+ g_16bit : boolean);
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ rxpcs_fab_o : out t_ep_internal_fabric;
+ rxpcs_fifo_almostfull_i : in std_logic;
+ rxpcs_busy_o : out std_logic;
+ rxpcs_timestamp_trigger_p_a_o : out std_logic;
+ rxpcs_timestamp_i : in std_logic_vector(31 downto 0);
+ rxpcs_timestamp_stb_i : in std_logic;
+ rxpcs_timestamp_valid_i : in std_logic;
+ txpcs_fab_i : in t_ep_internal_fabric;
+ txpcs_error_o : out std_logic;
+ txpcs_busy_o : out std_logic;
+ txpcs_dreq_o : out std_logic;
+ txpcs_timestamp_trigger_p_a_o : out std_logic;
+ link_ok_o : out std_logic;
+ link_ctr_i : in std_logic := '1';
+ serdes_rst_o : out std_logic;
+ serdes_syncen_o : out std_logic;
+ serdes_loopen_o : out std_logic;
+ serdes_enable_o : out std_logic;
+ serdes_tx_clk_i : in std_logic;
+ serdes_tx_data_o : out std_logic_vector(15 downto 0);
+ serdes_tx_k_o : out std_logic_vector(1 downto 0);
+ serdes_tx_disparity_i : in std_logic;
+ serdes_tx_enc_err_i : in std_logic;
+ serdes_rx_clk_i : in std_logic;
+ serdes_rx_data_i : in std_logic_vector(15 downto 0);
+ serdes_rx_k_i : in std_logic_vector(1 downto 0);
+ serdes_rx_enc_err_i : in std_logic;
+ serdes_rx_bitslide_i : in std_logic_vector(4 downto 0);
+ rmon_o : out t_rmon_triggers;
+ mdio_addr_i : in std_logic_vector(15 downto 0);
+ mdio_data_i : in std_logic_vector(15 downto 0);
+ mdio_data_o : out std_logic_vector(15 downto 0);
+ mdio_stb_i : in std_logic;
+ mdio_rw_i : in std_logic;
+ mdio_ready_o : out std_logic;
+ dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
+ dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
+ nice_dbg_o : out t_dbg_ep_pcs);
+ end component;
+
+ component ep_tx_pcs_8bit
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ pcs_fab_i : in t_ep_internal_fabric;
+ pcs_error_o : out std_logic;
+ pcs_busy_o : out std_logic;
+ pcs_dreq_o : out std_logic;
+ mdio_mcr_pdown_i : in std_logic;
+ mdio_wr_spec_tx_cal_i : in std_logic;
+ an_tx_en_i : in std_logic;
+ an_tx_val_i : in std_logic_vector(15 downto 0);
+ timestamp_trigger_p_a_o : out std_logic;
+ rmon_tx_underrun : out std_logic;
+ phy_tx_clk_i : in std_logic;
+ phy_tx_data_o : out std_logic_vector(7 downto 0);
+ phy_tx_k_o : out std_logic;
+ phy_tx_disparity_i : in std_logic;
+ phy_tx_enc_err_i : in std_logic);
+ end component;
+
+ component ep_tx_pcs_16bit
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ pcs_fab_i : in t_ep_internal_fabric;
+ pcs_error_o : out std_logic;
+ pcs_busy_o : out std_logic;
+ pcs_dreq_o : out std_logic;
+ mdio_mcr_pdown_i : in std_logic;
+ mdio_wr_spec_tx_cal_i : in std_logic;
+ an_tx_en_i : in std_logic;
+ an_tx_val_i : in std_logic_vector(15 downto 0);
+ timestamp_trigger_p_a_o : out std_logic;
+ rmon_tx_underrun : out std_logic;
+ phy_tx_clk_i : in std_logic;
+ phy_tx_data_o : out std_logic_vector(15 downto 0);
+ phy_tx_k_o : out std_logic_vector(1 downto 0);
+ phy_tx_disparity_i : in std_logic;
+ phy_tx_enc_err_i : in std_logic;
+ dbg_wr_count_o : out std_logic_vector(5+4 downto 0);
+ dbg_rd_count_o : out std_logic_vector(5+4 downto 0));
+ end component;
+
+ component ep_rx_pcs_8bit
generic (
g_simulation : boolean);
port (
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- rxpcs_fab_o : out t_ep_internal_fabric;
- rxpcs_busy_o : out std_logic;
- rxpcs_dreq_i : in std_logic;
- rxpcs_timestamp_stb_p_o : out std_logic;
- txpcs_fab_i : in t_ep_internal_fabric;
- txpcs_error_o : out std_logic;
- txpcs_busy_o : out std_logic;
- txpcs_dreq_o : out std_logic;
- txpcs_timestamp_stb_p_o : out std_logic;
- link_ok_o : out std_logic;
- serdes_rst_o : out std_logic;
- serdes_syncen_o : out std_logic;
- serdes_loopen_o : out std_logic;
- serdes_prbsen_o : out std_logic;
- serdes_enable_o : out std_logic;
- serdes_tx_clk_i : in std_logic;
- serdes_tx_data_o : out std_logic_vector(7 downto 0);
- serdes_tx_k_o : out std_logic;
- serdes_tx_disparity_i : in std_logic;
- serdes_tx_enc_err_i : in std_logic;
- serdes_rx_data_i : in std_logic_vector(7 downto 0);
- serdes_rx_clk_i : in std_logic;
- serdes_rx_k_i : in std_logic;
- serdes_rx_enc_err_i : in std_logic;
- serdes_rx_bitslide_i : in std_logic_vector(3 downto 0);
- rmon_o : out t_rmon_triggers;
- mdio_addr_i : in std_logic_vector(15 downto 0);
- mdio_data_i : in std_logic_vector(15 downto 0);
- mdio_data_o : out std_logic_vector(15 downto 0);
- mdio_stb_i : in std_logic;
- mdio_rw_i : in std_logic;
- mdio_ready_o : out std_logic);
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ pcs_fifo_almostfull_i : in std_logic;
+ pcs_busy_o : out std_logic;
+ pcs_fab_o : out t_ep_internal_fabric;
+ timestamp_trigger_p_a_o : out std_logic; -- strobe for RX timestamping
+ timestamp_i : in std_logic_vector(31 downto 0);
+ timestamp_stb_i : in std_logic;
+ timestamp_valid_i : in std_logic;
+ phy_rdy_i : in std_logic;
+ phy_rx_clk_i : in std_logic;
+ phy_rx_data_i : in std_logic_vector(7 downto 0);
+ phy_rx_k_i : in std_logic;
+ phy_rx_enc_err_i : in std_logic;
+ mdio_mcr_pdown_i : in std_logic;
+ mdio_wr_spec_cal_crst_i : in std_logic;
+ mdio_wr_spec_rx_cal_stat_o : out std_logic;
+ synced_o : out std_logic;
+ sync_lost_o : out std_logic;
+ an_rx_en_i : in std_logic;
+ an_rx_val_o : out std_logic_vector(15 downto 0);
+ an_rx_valid_o : out std_logic;
+ an_idle_match_o : out std_logic;
+ rmon_rx_overrun : out std_logic;
+ rmon_rx_inv_code : out std_logic;
+ rmon_rx_sync_lost : out std_logic);
end component;
- component ep_rmon_counters
+ component ep_rx_pcs_16bit
generic (
- g_num_counters : integer;
- g_ram_addr_width : integer);
+ g_simulation : boolean);
port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- cntr_rst_i : in std_logic;
- cntr_pulse_i : in std_logic_vector(g_num_counters-1 downto 0);
- ram_addr_o : out std_logic_vector(g_ram_addr_width-1 downto 0);
- ram_data_i : in std_logic_vector(31 downto 0);
- ram_data_o : out std_logic_vector(31 downto 0);
- ram_wr_o : out std_logic;
- cntr_overflow_o : out std_logic);
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ pcs_fifo_almostfull_i : in std_logic;
+ pcs_busy_o : out std_logic;
+ pcs_fab_o : out t_ep_internal_fabric;
+ timestamp_trigger_p_a_o : out std_logic; -- strobe for RX timestamping
+ timestamp_i : in std_logic_vector(31 downto 0);
+ timestamp_stb_i : in std_logic;
+ timestamp_valid_i : in std_logic;
+ phy_rdy_i : in std_logic;
+ phy_rx_clk_i : in std_logic;
+ phy_rx_data_i : in std_logic_vector(15 downto 0);
+ phy_rx_k_i : in std_logic_vector(1 downto 0);
+ phy_rx_enc_err_i : in std_logic;
+ mdio_mcr_pdown_i : in std_logic;
+ mdio_wr_spec_cal_crst_i : in std_logic;
+ mdio_wr_spec_rx_cal_stat_o : out std_logic;
+ synced_o : out std_logic;
+ sync_lost_o : out std_logic;
+ an_rx_en_i : in std_logic;
+ an_rx_val_o : out std_logic_vector(15 downto 0);
+ an_rx_valid_o : out std_logic;
+ an_idle_match_o : out std_logic;
+ rmon_rx_overrun : out std_logic;
+ rmon_rx_inv_code : out std_logic;
+ rmon_rx_sync_lost : out std_logic;
+ nice_dbg_o : out t_dbg_ep_rxpcs);
+ end component;
+
+ component ep_autonegotiation
+ generic (
+ g_simulation : boolean);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ pcs_synced_i : in std_logic;
+ pcs_los_i : in std_logic;
+ pcs_link_ok_o : out std_logic;
+ an_idle_match_i : in std_logic;
+ an_rx_en_o : out std_logic;
+ an_rx_val_i : in std_logic_vector(15 downto 0);
+ an_rx_valid_i : in std_logic;
+ an_tx_en_o : out std_logic;
+ an_tx_val_o : out std_logic_vector(15 downto 0);
+ mdio_mcr_anrestart_i : in std_logic;
+ mdio_mcr_anenable_i : in std_logic;
+ mdio_msr_anegcomplete_o : out std_logic;
+ mdio_advertise_pause_i : in std_logic_vector(1 downto 0);
+ mdio_advertise_rfault_i : in std_logic_vector(1 downto 0);
+ mdio_lpa_full_o : out std_logic;
+ mdio_lpa_half_o : out std_logic;
+ mdio_lpa_pause_o : out std_logic_vector(1 downto 0);
+ mdio_lpa_rfault_o : out std_logic_vector(1 downto 0);
+ mdio_lpa_lpack_o : out std_logic;
+ mdio_lpa_npage_o : out std_logic);
+ end component;
+
+ component ep_pcs_tbi_mdio_wb
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(4 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ tx_clk_i : in std_logic;
+ rx_clk_i : in std_logic;
+ mdio_mcr_uni_en_o : out std_logic;
+ mdio_mcr_anrestart_o : out std_logic;
+ mdio_mcr_pdown_o : out std_logic;
+ mdio_mcr_anenable_o : out std_logic;
+ mdio_mcr_loopback_o : out std_logic;
+ mdio_mcr_reset_o : out std_logic;
+ mdio_msr_lstatus_i : in std_logic;
+ lstat_read_notify_o : out std_logic;
+ mdio_msr_rfault_i : in std_logic;
+ mdio_msr_anegcomplete_i : in std_logic;
+ mdio_advertise_pause_o : out std_logic_vector(1 downto 0);
+ mdio_advertise_rfault_o : out std_logic_vector(1 downto 0);
+ mdio_lpa_full_i : in std_logic;
+ mdio_lpa_half_i : in std_logic;
+ mdio_lpa_pause_i : in std_logic_vector(1 downto 0);
+ mdio_lpa_rfault_i : in std_logic_vector(1 downto 0);
+ mdio_lpa_lpack_i : in std_logic;
+ mdio_lpa_npage_i : in std_logic;
+ mdio_wr_spec_tx_cal_o : out std_logic;
+ mdio_wr_spec_rx_cal_stat_i : in std_logic;
+ mdio_wr_spec_cal_crst_o : out std_logic;
+ mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0));
end component;
component ep_tx_header_processor
@@ -220,27 +388,24 @@ package endpoint_private_pkg is
g_timestamp_bits_f : natural;
g_ref_clock_rate : integer);
port (
- clk_ref_i : in std_logic;
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- pps_csync_p1_i : in std_logic;
- tx_timestamp_stb_p_i : in std_logic;
- rx_timestamp_stb_p_i : in std_logic;
- txoob_fid_i : in std_logic_vector(16 - 1 downto 0);
- txoob_stb_p_i : in std_logic;
- rxoob_data_o : out std_logic_vector(47 downto 0);
- rxoob_valid_o : out std_logic;
- rxoob_ack_i : in std_logic;
- txtsu_port_id_o : out std_logic_vector(4 downto 0);
- txtsu_fid_o : out std_logic_vector(16 -1 downto 0);
- txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
- txtsu_valid_o : out std_logic;
- txtsu_ack_i : in std_logic;
- ep_tscr_en_txts_i : in std_logic;
- ep_tscr_en_rxts_i : in std_logic;
- ep_tscr_cs_start_i : in std_logic;
- ep_tscr_cs_done_o : out std_logic;
- ep_ecr_portid_i : in std_logic_vector(4 downto 0));
+ clk_ref_i : in std_logic;
+ clk_sys_i : in std_logic;
+ clk_rx_i : in std_logic;
+ rst_n_rx_i : in std_logic;
+ rst_n_ref_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ pps_csync_p1_i : in std_logic;
+ pps_valid_i : in std_logic;
+ tx_timestamp_trigger_p_a_i : in std_logic;
+ rx_timestamp_trigger_p_a_i : in std_logic;
+ rxts_timestamp_o : out std_logic_vector(31 downto 0);
+ rxts_timestamp_stb_o : out std_logic;
+ rxts_timestamp_valid_o : out std_logic;
+ txts_timestamp_o : out std_logic_vector(31 downto 0);
+ txts_timestamp_stb_o : out std_logic;
+ txts_timestamp_valid_o : out std_logic;
+ regs_i : in t_ep_out_registers;
+ regs_o : out t_ep_in_registers);
end component;
component ep_flow_control
@@ -281,23 +446,6 @@ package endpoint_private_pkg is
regs_i : in t_ep_in_registers);
end component;
- component ep_rx_bypass_queue
- generic (
- g_size : integer;
- g_width : integer);
- port (
- rst_n_i : in std_logic;
- clk_i : in std_logic;
- d_i : in std_logic_vector(g_width-1 downto 0);
- valid_i : in std_logic;
- dreq_o : out std_logic;
- q_o : out std_logic_vector(g_width-1 downto 0);
- valid_o : out std_logic;
- dreq_i : in std_logic;
- flush_i : in std_logic;
- purge_i : in std_logic);
- end component;
-
component ep_leds_controller
generic (
g_blink_period_log2 : integer);
@@ -328,21 +476,222 @@ package endpoint_private_pkg is
mem_data_i : in std_logic_vector(17 downto 0));
end component;
- component ep_tx_framer
+ component ep_rtu_header_extract
+ generic (
+ g_with_rtu : boolean);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ mbuf_is_pause_i : in std_logic;
+ vlan_class_i : in std_logic_vector(2 downto 0);
+ vlan_vid_i : in std_logic_vector(11 downto 0);
+ vlan_tag_done_i : in std_logic;
+ vlan_is_tagged_i : in std_logic;
+ rmon_drp_at_rtu_full_o: out std_logic;
+ rtu_rq_o : out t_ep_internal_rtu_request;
+ rtu_full_i : in std_logic;
+ rtu_rq_abort_o : out std_logic;
+ rtu_rq_valid_o : out std_logic);
+ end component;
+
+ component ep_rx_early_address_match
+ port (
+ clk_sys_i : in std_logic;
+ clk_rx_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ rst_n_rx_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ src_fab_o : out t_ep_internal_fabric;
+ match_done_o : out std_logic;
+ match_is_hp_o : out std_logic;
+ match_is_pause_o : out std_logic;
+ match_pause_quanta_o : out std_logic_vector(15 downto 0);
+ match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+ match_pause_p_o : out std_logic;
+ regs_i : in t_ep_out_registers);
+ end component;
+
+ component ep_clock_alignment_fifo
+ generic (
+ g_size : integer;
+ g_almostfull_threshold : integer);
+ port (
+ rst_n_rd_i : in std_logic;
+ clk_wr_i : in std_logic;
+ clk_rd_i : in std_logic;
+ dreq_i : in std_logic;
+ fab_i : in t_ep_internal_fabric;
+ fab_o : out t_ep_internal_fabric;
+ full_o : out std_logic;
+ empty_o : out std_logic;
+ almostfull_o : out std_logic;
+ pass_threshold_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
+ end component;
+
+ component ep_packet_filter
+ port (
+ clk_rx_i : in std_logic;
+ clk_sys_i : in std_logic;
+ rst_n_rx_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ src_fab_o : out t_ep_internal_fabric;
+ done_o : out std_logic;
+ pclass_o : out std_logic_vector(7 downto 0);
+ drop_o : out std_logic;
+ regs_i : in t_ep_out_registers);
+ end component;
+
+ component ep_rx_vlan_unit
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ tclass_o : out std_logic_vector(2 downto 0);
+ vid_o : out std_logic_vector(11 downto 0);
+ tag_done_o : out std_logic;
+ is_tagged_o : out std_logic;
+ regs_i : in t_ep_out_registers;
+ regs_o : out t_ep_in_registers);
+ end component;
+
+ component ep_rx_oob_insert
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ regs_i : in t_ep_out_registers);
+ end component;
+
+ component ep_rx_crc_size_check
+ generic (
+ g_use_new_crc : boolean := false);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ regs_i : in t_ep_out_registers;
+ rmon_pcs_err_o : out std_logic;
+ rmon_giant_o : out std_logic;
+ rmon_runt_o : out std_logic;
+ rmon_crc_err_o : out std_logic);
+ end component;
+
+ component ep_rx_wb_master
+ generic (
+ g_ignore_ack : boolean;
+ g_cyc_on_stall : boolean := false);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_wb_i : in t_wrf_source_in;
+ src_wb_o : out t_wrf_source_out);
+ end component;
+
+ component ep_rx_status_reg_insert
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ mbuf_valid_i : in std_logic;
+ mbuf_ack_o : out std_logic;
+ mbuf_drop_i : in std_logic;
+ mbuf_pclass_i : in std_logic_vector(7 downto 0);
+ mbuf_is_hp_i : in std_logic;
+ mbuf_is_pause_i : in std_logic;
+ rmon_pfilter_drop_o : out std_logic);
+ end component;
+
+ component ep_rx_buffer
+ generic (
+ g_size : integer;
+ g_with_fc : boolean := false);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ snk_fab_i : in t_ep_internal_fabric;
+ snk_dreq_o : out std_logic;
+ src_fab_o : out t_ep_internal_fabric;
+ src_dreq_i : in std_logic;
+ level_o : out std_logic_vector(7 downto 0);
+ full_o : out std_logic;
+ drop_req_i : in std_logic;
+ dropped_o : out std_logic;
+ regs_i : in t_ep_out_registers;
+ rmon_o : out t_rmon_triggers);
+ end component;
+
+
+ component ep_rx_path
+ generic (
+ g_with_vlans : boolean;
+ g_with_dpi_classifier : boolean;
+ g_with_rtu : boolean;
+ g_with_rx_buffer : boolean;
+ g_rx_buffer_size : integer;
+ g_use_new_crc : boolean);
+ port (
+ clk_sys_i : in std_logic;
+ clk_rx_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ rst_n_rx_i : in std_logic;
+ pcs_fab_i : in t_ep_internal_fabric;
+ pcs_fifo_almostfull_o : out std_logic;
+ pcs_busy_i : in std_logic;
+ src_wb_o : out t_wrf_source_out;
+ src_wb_i : in t_wrf_source_in;
+ fc_pause_p_o : out std_logic;
+ fc_pause_quanta_o : out std_logic_vector(15 downto 0);
+ fc_pause_prio_mask_o : out std_logic_vector(7 downto 0);
+ fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
+ rmon_o : out t_rmon_triggers;
+ regs_i : in t_ep_out_registers;
+ regs_o : out t_ep_in_registers;
+ pfilter_pclass_o : out std_logic_vector(7 downto 0);
+ pfilter_drop_o : out std_logic;
+ pfilter_done_o : out std_logic;
+ rtu_rq_o : out t_ep_internal_rtu_request;
+ rtu_full_i : in std_logic;
+ rtu_rq_valid_o : out std_logic;
+ rtu_rq_abort_o : out std_logic;
+ nice_dbg_o : out t_dbg_ep_rxpath);
+ end component;
+
+ component ep_tx_path
generic (
g_with_vlans : boolean;
- g_with_packet_injection : boolean;
g_with_timestamper : boolean;
- g_force_gap_length : integer);
+ g_with_packet_injection : boolean;
+ g_force_gap_length : integer;
+ g_runt_padding : boolean;
+ g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- pcs_busy_i : in std_logic;
+ pcs_fab_o : out t_ep_internal_fabric;
pcs_error_i : in std_logic;
- wb_snk_i : in t_wrf_sink_in;
- wb_snk_o : out t_wrf_sink_out;
+ pcs_busy_i : in std_logic;
+ pcs_dreq_i : in std_logic;
+ snk_i : in t_wrf_sink_in;
+ snk_o : out t_wrf_sink_out;
fc_pause_req_i : in std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_ready_o : out std_logic;
@@ -355,7 +704,14 @@ package endpoint_private_pkg is
txtsu_ack_i : in std_logic;
txts_timestamp_i : in std_logic_vector(31 downto 0);
txts_timestamp_valid_i : in std_logic;
- regs_i : in t_ep_out_registers);
+ inject_req_i : in std_logic := '0';
+ inject_ready_o : out std_logic;
+ inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
+ inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
+ ep_ctrl_i : in std_logic := '1';
+ regs_i : in t_ep_out_registers;
+ regs_o : out t_ep_in_registers;
+ dbg_o : out std_logic_vector(33 downto 0));
end component;
component ep_tx_crc_inserter
diff --git a/modules/wr_endpoint/ep_1000basex_pcs.vhd b/modules/wr_endpoint/ep_1000basex_pcs.vhd
index 59a7ae6d41d2e8696dde9a9f4236f194d3871d26..f5ceb85eb221ae90af4a2294fac55874b959c420 100644
--- a/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/modules/wr_endpoint/ep_1000basex_pcs.vhd
@@ -188,182 +188,6 @@ end ep_1000basex_pcs;
architecture rtl of ep_1000basex_pcs is
- component ep_tx_pcs_8bit
- port (
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- pcs_fab_i : in t_ep_internal_fabric;
- pcs_error_o : out std_logic;
- pcs_busy_o : out std_logic;
- pcs_dreq_o : out std_logic;
- mdio_mcr_pdown_i : in std_logic;
- mdio_wr_spec_tx_cal_i : in std_logic;
- an_tx_en_i : in std_logic;
- an_tx_val_i : in std_logic_vector(15 downto 0);
- timestamp_trigger_p_a_o : out std_logic;
- rmon_tx_underrun : out std_logic;
- phy_tx_clk_i : in std_logic;
- phy_tx_data_o : out std_logic_vector(7 downto 0);
- phy_tx_k_o : out std_logic;
- phy_tx_disparity_i : in std_logic;
- phy_tx_enc_err_i : in std_logic);
- end component;
-
- component ep_tx_pcs_16bit
- port (
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- pcs_fab_i : in t_ep_internal_fabric;
- pcs_error_o : out std_logic;
- pcs_busy_o : out std_logic;
- pcs_dreq_o : out std_logic;
- mdio_mcr_pdown_i : in std_logic;
- mdio_wr_spec_tx_cal_i : in std_logic;
- an_tx_en_i : in std_logic;
- an_tx_val_i : in std_logic_vector(15 downto 0);
- timestamp_trigger_p_a_o : out std_logic;
- rmon_tx_underrun : out std_logic;
- phy_tx_clk_i : in std_logic;
- phy_tx_data_o : out std_logic_vector(15 downto 0);
- phy_tx_k_o : out std_logic_vector(1 downto 0);
- phy_tx_disparity_i : in std_logic;
- phy_tx_enc_err_i : in std_logic;
- dbg_wr_count_o : out std_logic_vector(5+4 downto 0);
- dbg_rd_count_o : out std_logic_vector(5+4 downto 0)
-);
- end component;
-
- component ep_rx_pcs_8bit
- generic (
- g_simulation : boolean);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- pcs_fifo_almostfull_i : in std_logic;
- pcs_busy_o : out std_logic;
- pcs_fab_o : out t_ep_internal_fabric;
- timestamp_trigger_p_a_o : out std_logic; -- strobe for RX timestamping
- timestamp_i : in std_logic_vector(31 downto 0);
- timestamp_stb_i : in std_logic;
- timestamp_valid_i : in std_logic;
- phy_rx_clk_i : in std_logic;
- phy_rx_data_i : in std_logic_vector(7 downto 0);
- phy_rx_k_i : in std_logic;
- phy_rx_enc_err_i : in std_logic;
- mdio_mcr_pdown_i : in std_logic;
- mdio_wr_spec_cal_crst_i : in std_logic;
- mdio_wr_spec_rx_cal_stat_o : out std_logic;
- synced_o : out std_logic;
- sync_lost_o : out std_logic;
- an_rx_en_i : in std_logic;
- an_rx_val_o : out std_logic_vector(15 downto 0);
- an_rx_valid_o : out std_logic;
- an_idle_match_o : out std_logic;
- rmon_rx_overrun : out std_logic;
- rmon_rx_inv_code : out std_logic;
- rmon_rx_sync_lost : out std_logic);
- end component;
-
- component ep_rx_pcs_16bit
- generic (
- g_simulation : boolean);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- pcs_fifo_almostfull_i : in std_logic;
- pcs_busy_o : out std_logic;
- pcs_fab_o : out t_ep_internal_fabric;
- timestamp_trigger_p_a_o : out std_logic; -- strobe for RX timestamping
- timestamp_i : in std_logic_vector(31 downto 0);
- timestamp_stb_i : in std_logic;
- timestamp_valid_i : in std_logic;
- phy_rx_clk_i : in std_logic;
- phy_rx_data_i : in std_logic_vector(15 downto 0);
- phy_rx_k_i : in std_logic_vector(1 downto 0);
- phy_rx_enc_err_i : in std_logic;
- mdio_mcr_pdown_i : in std_logic;
- mdio_wr_spec_cal_crst_i : in std_logic;
- mdio_wr_spec_rx_cal_stat_o : out std_logic;
- synced_o : out std_logic;
- sync_lost_o : out std_logic;
- an_rx_en_i : in std_logic;
- an_rx_val_o : out std_logic_vector(15 downto 0);
- an_rx_valid_o : out std_logic;
- an_idle_match_o : out std_logic;
- rmon_rx_overrun : out std_logic;
- rmon_rx_inv_code : out std_logic;
- rmon_rx_sync_lost : out std_logic;
- nice_dbg_o : out t_dbg_ep_rxpcs);
- end component;
-
-
- component ep_pcs_tbi_mdio_wb
- port (
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- wb_adr_i : in std_logic_vector(4 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_dat_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_stall_o : out std_logic;
- tx_clk_i : in std_logic;
- rx_clk_i : in std_logic;
- mdio_mcr_uni_en_o : out std_logic;
- mdio_mcr_anrestart_o : out std_logic;
- mdio_mcr_pdown_o : out std_logic;
- mdio_mcr_anenable_o : out std_logic;
- mdio_mcr_loopback_o : out std_logic;
- mdio_mcr_reset_o : out std_logic;
- mdio_msr_lstatus_i : in std_logic;
- lstat_read_notify_o : out std_logic;
- mdio_msr_rfault_i : in std_logic;
- mdio_msr_anegcomplete_i : in std_logic;
- mdio_advertise_pause_o : out std_logic_vector(1 downto 0);
- mdio_advertise_rfault_o : out std_logic_vector(1 downto 0);
- mdio_lpa_full_i : in std_logic;
- mdio_lpa_half_i : in std_logic;
- mdio_lpa_pause_i : in std_logic_vector(1 downto 0);
- mdio_lpa_rfault_i : in std_logic_vector(1 downto 0);
- mdio_lpa_lpack_i : in std_logic;
- mdio_lpa_npage_i : in std_logic;
- mdio_wr_spec_tx_cal_o : out std_logic;
- mdio_wr_spec_rx_cal_stat_i : in std_logic;
- mdio_wr_spec_cal_crst_o : out std_logic;
- mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0));
- end component;
-
- component ep_autonegotiation
- generic (
- g_simulation : boolean);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- pcs_synced_i : in std_logic;
- pcs_los_i : in std_logic;
- pcs_link_ok_o : out std_logic;
- an_idle_match_i : in std_logic;
- an_rx_en_o : out std_logic;
- an_rx_val_i : in std_logic_vector(15 downto 0);
- an_rx_valid_i : in std_logic;
- an_tx_en_o : out std_logic;
- an_tx_val_o : out std_logic_vector(15 downto 0);
- mdio_mcr_anrestart_i : in std_logic;
- mdio_mcr_anenable_i : in std_logic;
- mdio_msr_anegcomplete_o : out std_logic;
- mdio_advertise_pause_i : in std_logic_vector(1 downto 0);
- mdio_advertise_rfault_i : in std_logic_vector(1 downto 0);
- mdio_lpa_full_o : out std_logic;
- mdio_lpa_half_o : out std_logic;
- mdio_lpa_pause_o : out std_logic_vector(1 downto 0);
- mdio_lpa_rfault_o : out std_logic_vector(1 downto 0);
- mdio_lpa_lpack_o : out std_logic;
- mdio_lpa_npage_o : out std_logic);
- end component;
-
signal mdio_mcr_uni_en : std_logic;
signal mdio_mcr_anrestart : std_logic;
signal mdio_mcr_pdown : std_logic;
diff --git a/modules/wr_endpoint/ep_rx_path.vhd b/modules/wr_endpoint/ep_rx_path.vhd
index f35dec7193b29e8edb37f41a3fa40ef085100d11..e8a244ed0e5b5d0994f2d5116abc91591b6a724c 100644
--- a/modules/wr_endpoint/ep_rx_path.vhd
+++ b/modules/wr_endpoint/ep_rx_path.vhd
@@ -114,169 +114,6 @@ end ep_rx_path;
architecture behavioral of ep_rx_path is
- component ep_rtu_header_extract
- generic (
- g_with_rtu : boolean);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- mbuf_is_pause_i : in std_logic;
- vlan_class_i : in std_logic_vector(2 downto 0);
- vlan_vid_i : in std_logic_vector(11 downto 0);
- vlan_tag_done_i : in std_logic;
- vlan_is_tagged_i : in std_logic;
- rmon_drp_at_rtu_full_o: out std_logic;
- rtu_rq_o : out t_ep_internal_rtu_request;
- rtu_full_i : in std_logic;
- rtu_rq_abort_o : out std_logic;
- rtu_rq_valid_o : out std_logic);
- end component;
-
- component ep_rx_early_address_match
- port (
- clk_sys_i : in std_logic;
- clk_rx_i : in std_logic;
- rst_n_sys_i : in std_logic;
- rst_n_rx_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- src_fab_o : out t_ep_internal_fabric;
- match_done_o : out std_logic;
- match_is_hp_o : out std_logic;
- match_is_pause_o : out std_logic;
- match_pause_quanta_o : out std_logic_vector(15 downto 0);
- match_pause_prio_mask_o : out std_logic_vector(7 downto 0);
- match_pause_p_o : out std_logic;
- regs_i : in t_ep_out_registers);
- end component;
-
- component ep_clock_alignment_fifo
- generic (
- g_size : integer;
- g_almostfull_threshold : integer);
- port (
- rst_n_rd_i : in std_logic;
- clk_wr_i : in std_logic;
- clk_rd_i : in std_logic;
- dreq_i : in std_logic;
- fab_i : in t_ep_internal_fabric;
- fab_o : out t_ep_internal_fabric;
- full_o : out std_logic;
- empty_o : out std_logic;
- almostfull_o : out std_logic;
- pass_threshold_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
- end component;
-
- component ep_packet_filter
- port (
- clk_rx_i : in std_logic;
- clk_sys_i : in std_logic;
- rst_n_rx_i : in std_logic;
- rst_n_sys_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- src_fab_o : out t_ep_internal_fabric;
- done_o : out std_logic;
- pclass_o : out std_logic_vector(7 downto 0);
- drop_o : out std_logic;
- regs_i : in t_ep_out_registers);
- end component;
-
- component ep_rx_vlan_unit
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- tclass_o : out std_logic_vector(2 downto 0);
- vid_o : out std_logic_vector(11 downto 0);
- tag_done_o : out std_logic;
- is_tagged_o : out std_logic;
- regs_i : in t_ep_out_registers;
- regs_o : out t_ep_in_registers);
- end component;
-
- component ep_rx_oob_insert
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- regs_i : in t_ep_out_registers);
- end component;
-
- component ep_rx_crc_size_check
- generic (
- g_use_new_crc : boolean := false);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- regs_i : in t_ep_out_registers;
- rmon_pcs_err_o : out std_logic;
- rmon_giant_o : out std_logic;
- rmon_runt_o : out std_logic;
- rmon_crc_err_o : out std_logic);
- end component;
-
- component ep_rx_wb_master
- generic (
- g_ignore_ack : boolean;
- g_cyc_on_stall : boolean := false);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_wb_i : in t_wrf_source_in;
- src_wb_o : out t_wrf_source_out);
- end component;
-
- component ep_rx_status_reg_insert
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- mbuf_valid_i : in std_logic;
- mbuf_ack_o : out std_logic;
- mbuf_drop_i : in std_logic;
- mbuf_pclass_i : in std_logic_vector(7 downto 0);
- mbuf_is_hp_i : in std_logic;
- mbuf_is_pause_i : in std_logic;
- rmon_pfilter_drop_o : out std_logic);
- end component;
-
- component ep_rx_buffer
- generic (
- g_size : integer;
- g_with_fc : boolean := false);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- snk_fab_i : in t_ep_internal_fabric;
- snk_dreq_o : out std_logic;
- src_fab_o : out t_ep_internal_fabric;
- src_dreq_i : in std_logic;
- level_o : out std_logic_vector(7 downto 0);
- full_o : out std_logic;
- drop_req_i : in std_logic;
- dropped_o : out std_logic;
- regs_i : in t_ep_out_registers;
- rmon_o : out t_rmon_triggers);
- end component;
-
type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
signal state : t_rx_deframer_state;
@@ -572,32 +409,6 @@ begin -- behavioral
rxbuf_full <= '0';
end generate gen_without_rx_buffer;
--- U_RTU_Header_Extract : ep_rtu_header_extract
--- generic map (
--- g_with_rtu => g_with_rtu)
--- port map (
--- clk_sys_i => clk_sys_i,
--- rst_n_i => rst_n_sys_i,
--- snk_fab_i => fab_pipe(7),
--- snk_dreq_o => dreq_pipe(7),
--- src_fab_o => fab_pipe(8),
--- src_dreq_i => dreq_pipe(8),
--- mbuf_is_pause_i => mbuf_is_pause, -- this module is in the pipe before ep_rx_status_reg_insert,
--- -- however, we know that mbuf_is_pause is valid when it
--- -- is used by this module -- this is because blocks the pipe
--- -- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
--- -- at the end of the header... (clear ??:)
--- vlan_class_i => vlan_tclass,
--- vlan_vid_i => vlan_vid,
--- vlan_tag_done_i => vlan_tag_done,
--- vlan_is_tagged_i => vlan_is_tagged,
---
--- rmon_drp_at_rtu_full_o => rmon_o.rx_drop_at_rtu_full,
---
--- rtu_rq_o => rtu_rq_o,
--- rtu_full_i => rtu_full_i,
--- rtu_rq_valid_o => rtu_rq_valid);
-
U_Gen_Status : ep_rx_status_reg_insert
port map (
clk_sys_i => clk_sys_i,
diff --git a/modules/wr_endpoint/wr_endpoint.vhd b/modules/wr_endpoint/wr_endpoint.vhd
index f56eb92ebc0647b00867892b6ae7b60c780b785d..3548bd027f12da79240e5aa1b2867cb9a2af0141 100644
--- a/modules/wr_endpoint/wr_endpoint.vhd
+++ b/modules/wr_endpoint/wr_endpoint.vhd
@@ -308,9 +308,6 @@ architecture syn of wr_endpoint is
end if;
end f_pick_rate;
-
-
-
-------------------------------------------------------------------------------
component dmtd_phase_meas
generic (
@@ -328,154 +325,6 @@ architecture syn of wr_endpoint is
phase_meas_p_o : out std_logic);
end component;
-
- component ep_tx_path
- generic (
- g_with_vlans : boolean;
- g_with_timestamper : boolean;
- g_with_packet_injection : boolean;
- g_force_gap_length : integer;
- g_runt_padding : boolean;
- g_use_new_crc : boolean := false);
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- pcs_fab_o : out t_ep_internal_fabric;
- pcs_error_i : in std_logic;
- pcs_busy_i : in std_logic;
- pcs_dreq_i : in std_logic;
- snk_i : in t_wrf_sink_in;
- snk_o : out t_wrf_sink_out;
- fc_pause_req_i : in std_logic;
- fc_pause_delay_i : in std_logic_vector(15 downto 0);
- fc_pause_ready_o : out std_logic;
- fc_flow_enable_i : in std_logic;
- txtsu_port_id_o : out std_logic_vector(4 downto 0);
- txtsu_fid_o : out std_logic_vector(16 -1 downto 0);
- txtsu_ts_value_o : out std_logic_vector(28 + 4 - 1 downto 0);
- txtsu_ts_incorrect_o : out std_logic;
- txtsu_stb_o : out std_logic;
- txtsu_ack_i : in std_logic;
- txts_timestamp_i : in std_logic_vector(31 downto 0);
- txts_timestamp_valid_i : in std_logic;
- inject_req_i : in std_logic := '0';
- inject_ready_o : out std_logic;
- inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
- inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
- ep_ctrl_i : in std_logic := '1';
- regs_i : in t_ep_out_registers;
- regs_o : out t_ep_in_registers;
- dbg_o : out std_logic_vector(33 downto 0));
- end component;
-
- component ep_rx_path
- generic (
- g_with_vlans : boolean;
- g_with_dpi_classifier : boolean;
- g_with_rtu : boolean;
- g_with_rx_buffer : boolean;
- g_rx_buffer_size : integer;
- g_use_new_crc : boolean);
- port (
- clk_sys_i : in std_logic;
- clk_rx_i : in std_logic;
- rst_n_sys_i : in std_logic;
- rst_n_rx_i : in std_logic;
- pcs_fab_i : in t_ep_internal_fabric;
- pcs_fifo_almostfull_o : out std_logic;
- pcs_busy_i : in std_logic;
- src_wb_o : out t_wrf_source_out;
- src_wb_i : in t_wrf_source_in;
- fc_pause_p_o : out std_logic;
- fc_pause_quanta_o : out std_logic_vector(15 downto 0);
- fc_pause_prio_mask_o : out std_logic_vector(7 downto 0);
- fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
- rmon_o : out t_rmon_triggers;
- regs_i : in t_ep_out_registers;
- regs_o : out t_ep_in_registers;
- pfilter_pclass_o : out std_logic_vector(7 downto 0);
- pfilter_drop_o : out std_logic;
- pfilter_done_o : out std_logic;
- rtu_rq_o : out t_ep_internal_rtu_request;
- rtu_full_i : in std_logic;
- rtu_rq_valid_o : out std_logic;
- rtu_rq_abort_o : out std_logic;
- nice_dbg_o : out t_dbg_ep_rxpath);
- end component;
-
- component ep_1000basex_pcs
- generic (
- g_simulation : boolean;
- g_16bit : boolean);
- port (
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- rxpcs_fab_o : out t_ep_internal_fabric;
- rxpcs_fifo_almostfull_i : in std_logic;
- rxpcs_busy_o : out std_logic;
- rxpcs_timestamp_trigger_p_a_o : out std_logic;
- rxpcs_timestamp_i : in std_logic_vector(31 downto 0);
- rxpcs_timestamp_stb_i : in std_logic;
- rxpcs_timestamp_valid_i : in std_logic;
- txpcs_fab_i : in t_ep_internal_fabric;
- txpcs_error_o : out std_logic;
- txpcs_busy_o : out std_logic;
- txpcs_dreq_o : out std_logic;
- txpcs_timestamp_trigger_p_a_o : out std_logic;
- link_ok_o : out std_logic;
- link_ctr_i : in std_logic := '1';
- serdes_rst_o : out std_logic;
- serdes_syncen_o : out std_logic;
- serdes_loopen_o : out std_logic;
- serdes_enable_o : out std_logic;
- serdes_tx_clk_i : in std_logic;
- serdes_tx_data_o : out std_logic_vector(15 downto 0);
- serdes_tx_k_o : out std_logic_vector(1 downto 0);
- serdes_tx_disparity_i : in std_logic;
- serdes_tx_enc_err_i : in std_logic;
- serdes_rx_clk_i : in std_logic;
- serdes_rx_data_i : in std_logic_vector(15 downto 0);
- serdes_rx_k_i : in std_logic_vector(1 downto 0);
- serdes_rx_enc_err_i : in std_logic;
- serdes_rx_bitslide_i : in std_logic_vector(4 downto 0);
- rmon_o : out t_rmon_triggers;
- mdio_addr_i : in std_logic_vector(15 downto 0);
- mdio_data_i : in std_logic_vector(15 downto 0);
- mdio_data_o : out std_logic_vector(15 downto 0);
- mdio_stb_i : in std_logic;
- mdio_rw_i : in std_logic;
- mdio_ready_o : out std_logic;
- dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
- dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
- nice_dbg_o : out t_dbg_ep_pcs);
- end component;
-
- component ep_timestamping_unit
- generic (
- g_timestamp_bits_r : natural;
- g_timestamp_bits_f : natural;
- g_ref_clock_rate : integer);
- port (
- clk_ref_i : in std_logic;
- clk_sys_i : in std_logic;
- clk_rx_i : in std_logic;
- rst_n_rx_i : in std_logic;
- rst_n_ref_i : in std_logic;
- rst_n_sys_i : in std_logic;
- pps_csync_p1_i : in std_logic;
- pps_valid_i : in std_logic;
- tx_timestamp_trigger_p_a_i : in std_logic;
- rx_timestamp_trigger_p_a_i : in std_logic;
- rxts_timestamp_o : out std_logic_vector(31 downto 0);
- rxts_timestamp_stb_o : out std_logic;
- rxts_timestamp_valid_o : out std_logic;
- txts_timestamp_o : out std_logic_vector(31 downto 0);
- txts_timestamp_stb_o : out std_logic;
- txts_timestamp_valid_o : out std_logic;
- regs_i : in t_ep_out_registers;
- regs_o : out t_ep_in_registers);
- end component;
-
-------------------------------------------------------------------------------
-- TX FRAMER -> TX PCS signals
-------------------------------------------------------------------------------
@@ -513,22 +362,6 @@ architecture syn of wr_endpoint is
signal rxpcs_busy : std_logic;
signal rxpcs_fifo_almostfull : std_logic;
--------------------------------------------------------------------------------
--- RX deframer -> RX buffer signals
--------------------------------------------------------------------------------
-
- --signal rbuf_data : std_logic_vector(15 downto 0);
- --signal rbuf_ctrl : std_logic_vector(4-1 downto 0);
- --signal rbuf_sof_p : std_logic;
- --signal rbuf_eof_p : std_logic;
- --signal rbuf_error_p : std_logic;
- --signal rbuf_valid : std_logic;
- --signal rbuf_drop : std_logic;
- --signal rbuf_bytesel : std_logic;
-
- --signal rx_buffer_used : std_logic_vector(7 downto 0);
-
-
-------------------------------------------------------------------------------
-- WB slave signals
-------------------------------------------------------------------------------
@@ -548,18 +381,11 @@ architecture syn of wr_endpoint is
signal txfra_flow_enable : std_logic;
signal rxfra_pause_p : std_logic;
signal rxfra_pause_delay : std_logic_vector(15 downto 0);
- --signal rxbuf_threshold_hit : std_logic;
signal txfra_pause_req : std_logic;
signal txfra_pause_ready : std_logic;
signal txfra_pause_delay : std_logic_vector(15 downto 0);
- --signal rofifo_write, rofifo_full, oob_valid_d0 : std_logic;
-
- --signal phase_meas : std_logic_vector(31 downto 0);
- --signal phase_meas_p : std_logic;
- --signal validity_cntr : unsigned(1 downto 0);
-
signal link_ok : std_logic;
signal txfra_enable, rxfra_enable : std_logic;