diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v
old mode 100755
new mode 100644
index 7163b2af75818bf0d6669b17ccf5ee8f828ab26b..0b8e2fcf69e8dad374b879dd539ffe4f58e5e1a5
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_bit_sync.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_bit_synchronizer # (
+module gtwizard_ultrascale_v1_7_14_bit_synchronizer # (
parameter INITIALIZE = 5'b00000,
parameter FREQUENCY = 512
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
old mode 100755
new mode 100644
index d46cbf18205b42a354059a00686687995703bcc6..57c8666b6191c74a7119dbac0a118e95740449f0
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gte4_drp_arb.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gte4_drp_arb
+module gtwizard_ultrascale_v1_7_14_gte4_drp_arb
#(
parameter [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C,
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v
old mode 100755
new mode 100644
index 44ea6f3b009530e53f8f23487e8b0b7450a21639..d0d51b5ea3d3641016b7b70cfdf282d298100cd5
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal_freq_counter # (
+module gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
@@ -117,7 +117,7 @@ module gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal_freq_counter # (
wire testclk_rst_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_testclk_rst_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v
old mode 100755
new mode 100644
index dab018cfe96fd1dc4b44314119188621bd7e9780..cd515c1a8ddeca1379aa894e0072918eb7c55969
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal # (
+module gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal # (
parameter REVISION = 2
)(
// control signals
@@ -189,45 +189,45 @@ module gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal # (
);
wire reset_in_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_resetin_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_inst (
.clk_in (CLK_IN),
.rst_in (RESET_IN),
.rst_out (reset_in_sync)
);
wire gthe3_cplllock_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_cplllock_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_cplllock_inst (
.clk_in (CLK_IN),
.i_in (GTHE3_CPLLLOCK_IN),
.o_out (gthe3_cplllock_sync)
);
wire user_txprogdivreset_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
.clk_in (CLK_IN),
.i_in (USER_TXPROGDIVRESET_IN),
.o_out (user_txprogdivreset_sync)
);
wire gthe3_txprgdivresetdone_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTHE3_TXPRGDIVRESETDONE_IN),
.o_out (gthe3_txprgdivresetdone_sync)
);
wire [2:0] user_txoutclksel_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[0]),
.o_out (user_txoutclksel_sync[0])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[1]),
.o_out (user_txoutclksel_sync[1])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[2]),
.o_out (user_txoutclksel_sync[2])
@@ -268,7 +268,7 @@ module gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal # (
wire [17:0] txoutclk_freq_cnt;
reg freq_counter_rst = 1'b1;
wire freq_cnt_done;
- gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
+ gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
(
.freq_cnt_o(txoutclk_freq_cnt),
.done_o(freq_cnt_done),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v
old mode 100755
new mode 100644
index 8ee8defbd01ea0ad49cca561bffe8dadf109a28f..d18bdf75cb333e1e4c1eaad43bdefd3f7958fa92
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_freq_counter # (
+module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
@@ -117,7 +117,7 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_freq_counter # (
wire testclk_rst_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_testclk_rst_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v
old mode 100755
new mode 100644
index c1131316564395fea71c449aff37f1745c3f1da1..f42e5ea0f373a36c96da8ddb902cee1556f26bc0
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
+module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal # (
parameter integer C_RX_PLL_TYPE = 0,
parameter integer C_TX_PLL_TYPE = 0,
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
@@ -64,7 +64,6 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
)(
// control signals
input wire [17:0] TXOUTCLK_PERIOD_IN,
- input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
input wire [17:0] CNT_TOL_IN,
input wire [15:0] FREQ_COUNT_WINDOW_IN,
// User Interface
@@ -173,7 +172,7 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx;
wire cal_on_tx_reset_in_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_resetin_tx_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_tx_inst (
.clk_in (CLK_IN),
.rst_in (cal_on_tx_reset_in),
.rst_out (cal_on_tx_reset_in_sync)
@@ -184,31 +183,30 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx;
wire cal_on_rx_reset_in_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_resetin_rx_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_resetin_rx_inst (
.clk_in (CLK_IN),
.rst_in (cal_on_rx_reset_in),
.rst_out (cal_on_rx_reset_in_sync)
);
wire drprst_in_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_drprst_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_drprst_inst (
.clk_in (CLK_IN),
.i_in (DRPRST_IN),
.o_out (drprst_in_sync)
);
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx #
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_tx #
(
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
.C_PCIE_ENABLE(C_PCIE_ENABLE),
.C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ)
- ) gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx_i
+ ) gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_tx_i
(
// control signals
.TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
- .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN),
.CNT_TOL_IN(CNT_TOL_IN),
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
// User Interface
@@ -244,17 +242,16 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
.DONE(tx_done)
);
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_rx #
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_rx #
(
.C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS),
.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP),
.CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX),
.C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY)
- ) gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_rx_i
+ ) gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_rx_i
(
// control signals
.RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN),
- .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN),
.CNT_TOL_IN(CNT_TOL_IN),
.FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN),
// User Interface
@@ -312,7 +309,7 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
// DRP ARBITER
//----------------------------------------------------------------------------------------------
- gtwizard_ultrascale_v1_7_7_gte4_drp_arb #
+ gtwizard_ultrascale_v1_7_14_gte4_drp_arb #
(
.ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL),
.ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG),
@@ -323,7 +320,7 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal # (
.C_NUM_CLIENTS(3),
.C_ADDR_WIDTH(10),
.C_DATA_WIDTH(16)
- ) gtwizard_ultrascale_v1_7_7_gte4_drp_arb_i
+ ) gtwizard_ultrascale_v1_7_14_gte4_drp_arb_i
(
.DCLK_I (CLK_IN),
.RESET_I (drprst_in_sync),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v
old mode 100755
new mode 100644
index fb6333b5dd5048d23bbe76cfddcd5437cb4e8f7c..d9e901bb5c76cd391d136c3605fc047a88e1457a
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_rx # (
+module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_rx # (
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter CPLL_CAL_ONLY_TX = 1,
@@ -60,7 +60,6 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_rx # (
)(
// control signals
input wire [17:0] RXOUTCLK_PERIOD_IN,
- input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
input wire [17:0] CNT_TOL_IN,
input wire [15:0] FREQ_COUNT_WINDOW_IN,
// User Interface
@@ -259,21 +258,21 @@ begin: gen_cal_rx_en
);
wire gthe4_cplllock_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_cplllock_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_cplllock_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_CPLLLOCK_IN),
.o_out (gthe4_cplllock_sync)
);
wire gthe4_rxpmaresetdone_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxpmaresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxpmaresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_RXPMARESETDONE_IN),
.o_out (gthe4_rxpmaresetdone_sync)
);
wire gthe4_rxprgdivresetdone_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxprgdivresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxprgdivresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_RXPRGDIVRESETDONE_IN),
.o_out (gthe4_rxprgdivresetdone_sync)
@@ -301,7 +300,7 @@ begin: gen_cal_rx_en
wire [17:0] rxoutclk_freq_cnt;
reg freq_counter_rst = 1'b1;
wire freq_cnt_done;
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_freq_counter U_RXOUTCLK_FREQ_COUNTER
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_freq_counter U_RXOUTCLK_FREQ_COUNTER
(
.freq_cnt_o(rxoutclk_freq_cnt),
.done_o(freq_cnt_done),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v
old mode 100755
new mode 100644
index 071ba9b53c6ad64fae96ab57d6b202f0cceb4e9d..7aed79a775cafe8dc78fe0f881754d61920963eb
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx # (
+module gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_tx # (
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter C_FREERUN_FREQUENCY = 100,
@@ -62,7 +62,6 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx # (
)(
// control signals
input wire [17:0] TXOUTCLK_PERIOD_IN,
- input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
input wire [17:0] CNT_TOL_IN,
input wire [15:0] FREQ_COUNT_WINDOW_IN,
// User Interface
@@ -223,38 +222,38 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx # (
);
wire gthe4_cplllock_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_cplllock_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_cplllock_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_CPLLLOCK_IN),
.o_out (gthe4_cplllock_sync)
);
wire user_txprogdivreset_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
.clk_in (CLK_IN),
.i_in (USER_TXPROGDIVRESET_IN),
.o_out (user_txprogdivreset_sync)
);
wire gthe4_txprgdivresetdone_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTHE4_TXPRGDIVRESETDONE_IN),
.o_out (gthe4_txprgdivresetdone_sync)
);
wire [2:0] user_txoutclksel_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[0]),
.o_out (user_txoutclksel_sync[0])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[1]),
.o_out (user_txoutclksel_sync[1])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[2]),
.o_out (user_txoutclksel_sync[2])
@@ -306,7 +305,7 @@ module gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_tx # (
wire [17:0] txoutclk_freq_cnt;
reg freq_counter_rst = 1'b1;
wire freq_cnt_done;
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
(
.freq_cnt_o(txoutclk_freq_cnt),
.done_o(freq_cnt_done),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v
old mode 100755
new mode 100644
index 36009f835dc38f6adfe2f04326ed132f7e285b72..7e5732052aaac3c16610c5a1675d7db63f5d1078
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_delay_powergood # (
+module gtwizard_ultrascale_v1_7_14_gthe4_delay_powergood # (
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
parameter C_PCIE_ENABLE = "FALSE"
)(
@@ -84,10 +84,10 @@ begin : gen_powergood_nodelay
end
else
begin: gen_powergood_delay
- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] wait_cnt;
- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
- (* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
+ (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r = 5'd0;
+ (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg [8:0] wait_cnt;
+ (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg int_pwr_on_fsm = 1'b0;
+ (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) (* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
wire intclk_rrst_n;
//--------------------------------------------------------------------------
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v
old mode 100755
new mode 100644
index 68a27d8709ef0ae9ad1985f2be1380139ca6f802..372fd706f0e30103ab28c135a60e8b5771a0e51f
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
parameter integer P_BUFFER_BYPASS_MODE = 0,
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
@@ -144,7 +144,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
wire gtwiz_buffbypass_rx_resetdone_sync_int;
- gtwizard_ultrascale_v1_7_7_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
+ gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.rst_in (gtwiz_buffbypass_rx_resetdone_in),
.rst_out (gtwiz_buffbypass_rx_resetdone_sync_int)
@@ -169,7 +169,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
wire gtwiz_buffbypass_rx_master_syncdone_sync_int;
wire gtwiz_buffbypass_rx_master_syncdone_sync_re;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_mastersyncdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_mastersyncdone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.i_in (rxsyncdone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_rx_master_syncdone_sync_int)
@@ -184,7 +184,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
// Synchronize the master channel's phase alignment completion output (RXPHALIGNDONE) into the local clock domain
wire gtwiz_buffbypass_rx_master_phaligndone_sync_int;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_masterphaligndone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_masterphaligndone_inst (
.clk_in (gtwiz_buffbypass_rx_clk_in),
.i_in (rxphaligndone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_rx_master_phaligndone_sync_int)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v
old mode 100755
new mode 100644
index 88e7ea9a29fad35e7ab9f98489551cb0a16c3e38..3468dc4d96f348c3eace8e5b98136045373ba366
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
parameter integer P_BUFFER_BYPASS_MODE = 0,
parameter integer P_TOTAL_NUMBER_OF_CHANNELS = 1,
@@ -157,7 +157,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
// start signal to the OR of this reset done indicator, and the synchronous buffer bypass procedure user request.
wire gtwiz_buffbypass_tx_resetdone_sync_int;
- gtwizard_ultrascale_v1_7_7_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
+ gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_resetdone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.rst_in (gtwiz_buffbypass_tx_resetdone_in),
.rst_out (gtwiz_buffbypass_tx_resetdone_sync_int)
@@ -182,7 +182,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
wire gtwiz_buffbypass_tx_master_syncdone_sync_int;
wire gtwiz_buffbypass_tx_master_syncdone_sync_re;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_master_syncdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_master_syncdone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.i_in (txsyncdone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_tx_master_syncdone_sync_int)
@@ -197,7 +197,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
// Synchronize the master channel's phase alignment completion output (TXPHALIGNDONE) into the local clock domain
wire gtwiz_buffbypass_tx_master_phaligndone_sync_int;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_master_phaligndone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_master_phaligndone_inst (
.clk_in (gtwiz_buffbypass_tx_clk_in),
.i_in (txphaligndone_in[P_MASTER_CHANNEL_POINTER]),
.o_out (gtwiz_buffbypass_tx_master_phaligndone_sync_int)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v
old mode 100755
new mode 100644
index 5d8eb3cd9f25b54402c6be2b86b9dc687ef5505c..98b43106e4d2391749dda372c1b919014fc232c3
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_reset.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
+module gtwizard_ultrascale_v1_7_14_gtwiz_reset # (
parameter real P_FREERUN_FREQUENCY = 200,
parameter integer P_USE_CPLL_CAL = 0,
@@ -113,7 +113,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the "reset all" input signal into the free-running clock domain
wire gtwiz_reset_all_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_all_in),
.rst_out (gtwiz_reset_all_sync)
@@ -121,7 +121,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the transceiver power good indicator
wire gtpowergood_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtpowergood_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtpowergood_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtpowergood_in),
.o_out (gtpowergood_sync)
@@ -262,7 +262,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
assign gtwiz_reset_tx_any = gtwiz_reset_tx_pll_and_datapath_in ||
gtwiz_reset_tx_pll_and_datapath_int ||
gtwiz_reset_tx_datapath_in;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_any_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_any_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_tx_any),
.rst_out (gtwiz_reset_tx_any_sync)
@@ -270,7 +270,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the OR of the user input and internal TX PLL and data path reset signals
wire gtwiz_reset_tx_pll_and_datapath_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_tx_pll_and_datapath_in || gtwiz_reset_tx_pll_and_datapath_int),
.rst_out (gtwiz_reset_tx_pll_and_datapath_sync)
@@ -278,7 +278,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Use another synchronizer to delay the above signal for purposes of its detection following reset
wire gtwiz_reset_tx_pll_and_datapath_dly;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_tx_pll_and_datapath_sync),
.o_out (gtwiz_reset_tx_pll_and_datapath_dly)
@@ -286,7 +286,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the TX data path reset user input
wire gtwiz_reset_tx_datapath_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_datapath_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_tx_datapath_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_tx_datapath_in),
.rst_out (gtwiz_reset_tx_datapath_sync)
@@ -294,7 +294,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Use another synchronizer to delay the above signal for purposes of its detection following reset
wire gtwiz_reset_tx_datapath_dly;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_tx_datapath_sync),
.o_out (gtwiz_reset_tx_datapath_dly)
@@ -302,7 +302,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the TX user clock active indicator
wire gtwiz_reset_userclk_tx_active_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_userclk_tx_active_in),
.o_out (gtwiz_reset_userclk_tx_active_sync)
@@ -310,7 +310,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the TX PLL lock indicator
wire plllock_tx_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_plllock_tx_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_plllock_tx_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (plllock_tx_in),
.o_out (plllock_tx_sync)
@@ -467,14 +467,14 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
end
// Hold the TX programmable divider in reset until the TX PLL has locked
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_txprogdivreset_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_txprogdivreset_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (~plllock_tx_in),
.rst_out (txprogdivreset_out)
);
// Synchronize the reset helper block TX reset done user output into the TXUSRCLK2 domain for user consumption
- gtwizard_ultrascale_v1_7_7_reset_inv_synchronizer reset_synchronizer_tx_done_inst (
+ gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_tx_done_inst (
.clk_in (txusrclk2_in),
.rst_in (gtwiz_reset_tx_done_int),
.rst_out (gtwiz_reset_tx_done_out)
@@ -506,7 +506,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
gtwiz_reset_rx_pll_and_datapath_int ||
gtwiz_reset_rx_datapath_in ||
gtwiz_reset_rx_datapath_int;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_any_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_any_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_rx_any),
.rst_out (gtwiz_reset_rx_any_sync)
@@ -514,7 +514,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the OR of the user input and internal RX PLL and data path reset signals
wire gtwiz_reset_rx_pll_and_datapath_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_rx_pll_and_datapath_in || gtwiz_reset_rx_pll_and_datapath_int),
.rst_out (gtwiz_reset_rx_pll_and_datapath_sync)
@@ -522,7 +522,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Use another synchronizer to delay the above signal for purposes of its detection following reset
wire gtwiz_reset_rx_pll_and_datapath_dly;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_rx_pll_and_datapath_sync),
.o_out (gtwiz_reset_rx_pll_and_datapath_dly)
@@ -530,7 +530,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the RX data path reset user input
wire gtwiz_reset_rx_datapath_sync;
- gtwizard_ultrascale_v1_7_7_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_datapath_inst (
+ gtwizard_ultrascale_v1_7_14_reset_synchronizer reset_synchronizer_gtwiz_reset_rx_datapath_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.rst_in (gtwiz_reset_rx_datapath_in || gtwiz_reset_rx_datapath_int),
.rst_out (gtwiz_reset_rx_datapath_sync)
@@ -538,7 +538,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Use another synchronizer to delay the above signal for purposes of its detection following reset
wire gtwiz_reset_rx_datapath_dly;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_rx_datapath_sync),
.o_out (gtwiz_reset_rx_datapath_dly)
@@ -546,7 +546,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the RX user clock active indicator
wire gtwiz_reset_userclk_rx_active_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_reset_userclk_rx_active_in),
.o_out (gtwiz_reset_userclk_rx_active_sync)
@@ -554,7 +554,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the RX PLL lock indicator
wire plllock_rx_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_plllock_rx_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_plllock_rx_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (plllock_rx_in),
.o_out (plllock_rx_sync)
@@ -562,7 +562,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
// Synchronize the RX CDR lock indicator
wire rxcdrlock_sync;
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxcdrlock_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxcdrlock_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (rxcdrlock_in),
.o_out (rxcdrlock_sync)
@@ -756,7 +756,7 @@ module gtwizard_ultrascale_v1_7_7_gtwiz_reset # (
assign gtwiz_reset_rx_cdr_stable_out = rxcdrlock_sync;
// Synchronize the reset helper block RX reset done user output into the RXUSRCLK2 domain for user consumption
- gtwizard_ultrascale_v1_7_7_reset_inv_synchronizer reset_synchronizer_rx_done_inst (
+ gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer reset_synchronizer_rx_done_inst (
.clk_in (rxusrclk2_in),
.rst_in (gtwiz_reset_rx_done_int),
.rst_out (gtwiz_reset_rx_done_out)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v
old mode 100755
new mode 100644
index 1dbc9d7088fa08173d93123047e07af2fb3ae270..0cf6cc822f9075a5e3b8b1bf3f05896ebe685a9b
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_userclk_rx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v
old mode 100755
new mode 100644
index 6e028822fe8f671bc9f97020d7fa850ad7223284..70e2633012e982566a035eb0e8f22e2bace8733b
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_userclk_tx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v
old mode 100755
new mode 100644
index 3d4cb6f810c57645c4a315b7a63ba4b446083ca1..a7ab424fc9a1c93866e9885c1b326362c5898c39
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_userdata_rx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_userdata_rx #(
parameter integer P_RX_USER_DATA_WIDTH = 32,
parameter integer P_RX_DATA_DECODING = 0,
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v
old mode 100755
new mode 100644
index d9e0a4334057f7d683d7ce88836175952de75846..64697332c8b7f7c87372b20f675ca4fb30ced7b6
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gtwiz_userdata_tx #(
+module gtwizard_ultrascale_v1_7_14_gtwiz_userdata_tx #(
parameter integer P_TX_USER_DATA_WIDTH = 32,
parameter integer P_TX_DATA_ENCODING = 0,
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v
old mode 100755
new mode 100644
index a1cd32946fbbfffd72d726a37739d7d7575bcb90..56d078e20d0b9426da65fd16c4b2b30e59d25140
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_inv_sync.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_reset_inv_synchronizer # (
+module gtwizard_ultrascale_v1_7_14_reset_inv_synchronizer # (
parameter FREQUENCY = 512
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v
old mode 100755
new mode 100644
index ffaef31c6d5a2ceb8a664f58d9fc77eaa69113ba..aa1db04c2e95a746f4d87298c0607e28569417c8
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/common/gtwizard_ultrascale_v1_7_reset_sync.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_reset_synchronizer # (
+module gtwizard_ultrascale_v1_7_14_reset_synchronizer # (
parameter FREQUENCY = 512
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
index 5d765a645f97906ad2637000b574fe94272d74f9..22dcb0ec78894fad5e43e435c586ed22c71231f0 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.v
@@ -1,4 +1,4 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -48,16 +48,16 @@
// IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7
-// IP Revision: 7
+// IP Revision: 14
-(* X_CORE_INFO = "gtwizard_ultrascale_2_gtwizard_top,Vivado 2019.2" *)
+(* X_CORE_INFO = "gtwizard_ultrascale_2_gtwizard_top,Vivado 2022.2" *)
(* CHECK_LICENSE_TYPE = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{}" *)
-(* CORE_GENERATION_INFO = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.7,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=1\
-,C_CPLL_VCO_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=2,C_GT_REV=57,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=1,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=1,C_LOCATE_RX_USER_CLOCKING=0,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=0,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0,\
-C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_ENA\
-BLE=1,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=1,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=1,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK\
-=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=16,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=1,C_TX_ENABLE=1,\
-C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=125.0000000,C_TX_OUTCLK_SOURCE=2,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=2,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=16,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
+(* CORE_GENERATION_INFO = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.7,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=\
+1,C_CPLL_VCO_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=2,C_GT_REV=57,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=1,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=1,C_LOCATE_RX_USER_CLOCKING=0,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=0,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0\
+,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_EN\
+ABLE=1,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=1,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=1,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCL\
+K=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=16,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=1,C_TX_ENABLE=1\
+,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=125.0000000,C_TX_OUTCLK_SOURCE=2,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=2,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=16,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gtwizard_ultrascale_2 (
gtwiz_userclk_tx_reset_in,
@@ -128,35 +128,35 @@ module gtwizard_ultrascale_2 (
txpmaresetdone_out
);
-(* mark_debug = "true" *) input wire [0 : 0] gtwiz_userclk_tx_reset_in;
+input wire [0 : 0] gtwiz_userclk_tx_reset_in;
output wire [0 : 0] gtwiz_userclk_tx_srcclk_out;
output wire [0 : 0] gtwiz_userclk_tx_usrclk_out;
output wire [0 : 0] gtwiz_userclk_tx_usrclk2_out;
-(* mark_debug = "true" *)output wire [0 : 0] gtwiz_userclk_tx_active_out;
-(* mark_debug = "true" *)input wire [0 : 0] gtwiz_userclk_rx_reset_in;
+output wire [0 : 0] gtwiz_userclk_tx_active_out;
+input wire [0 : 0] gtwiz_userclk_rx_reset_in;
output wire [0 : 0] gtwiz_userclk_rx_srcclk_out;
output wire [0 : 0] gtwiz_userclk_rx_usrclk_out;
output wire [0 : 0] gtwiz_userclk_rx_usrclk2_out;
-(* mark_debug = "true" *)output wire [0 : 0] gtwiz_userclk_rx_active_out;
-(* mark_debug = "true" *)input wire [0 : 0] gtwiz_buffbypass_tx_reset_in;
+output wire [0 : 0] gtwiz_userclk_rx_active_out;
+input wire [0 : 0] gtwiz_buffbypass_tx_reset_in;
input wire [0 : 0] gtwiz_buffbypass_tx_start_user_in;
output wire [0 : 0] gtwiz_buffbypass_tx_done_out;
output wire [0 : 0] gtwiz_buffbypass_tx_error_out;
-(* mark_debug = "true" *)input wire [0 : 0] gtwiz_buffbypass_rx_reset_in;
+input wire [0 : 0] gtwiz_buffbypass_rx_reset_in;
input wire [0 : 0] gtwiz_buffbypass_rx_start_user_in;
-(* mark_debug = "true" *)output wire [0 : 0] gtwiz_buffbypass_rx_done_out;
+output wire [0 : 0] gtwiz_buffbypass_rx_done_out;
output wire [0 : 0] gtwiz_buffbypass_rx_error_out;
input wire [0 : 0] gtwiz_reset_clk_freerun_in;
-(* mark_debug = "true" *)input wire [0 : 0] gtwiz_reset_all_in;
+input wire [0 : 0] gtwiz_reset_all_in;
input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in;
input wire [0 : 0] gtwiz_reset_tx_datapath_in;
input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in;
input wire [0 : 0] gtwiz_reset_rx_datapath_in;
output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out;
-(* mark_debug = "true" *)output wire [0 : 0] gtwiz_reset_tx_done_out;
-(* mark_debug = "true" *)output wire [0 : 0] gtwiz_reset_rx_done_out;
-(* mark_debug = "true" *)input wire [15 : 0] gtwiz_userdata_tx_in;
-(* mark_debug = "true" *)output wire [15 : 0] gtwiz_userdata_rx_out;
+output wire [0 : 0] gtwiz_reset_tx_done_out;
+output wire [0 : 0] gtwiz_reset_rx_done_out;
+input wire [15 : 0] gtwiz_userdata_tx_in;
+output wire [15 : 0] gtwiz_userdata_rx_out;
input wire [9 : 0] drpaddr_in;
input wire [0 : 0] drpclk_in;
input wire [15 : 0] drpdi_in;
@@ -167,7 +167,7 @@ input wire [0 : 0] gthrxn_in;
input wire [0 : 0] gthrxp_in;
input wire [0 : 0] gtrefclk0_in;
input wire [0 : 0] rx8b10ben_in;
-(* mark_debug = "true" *)input wire [0 : 0] rxcommadeten_in;
+input wire [0 : 0] rxcommadeten_in;
input wire [0 : 0] rxlpmen_in;
input wire [0 : 0] rxmcommaalignen_in;
input wire [0 : 0] rxpcommaalignen_in;
@@ -184,7 +184,7 @@ output wire [15 : 0] drpdo_out;
output wire [0 : 0] drprdy_out;
output wire [0 : 0] gthtxn_out;
output wire [0 : 0] gthtxp_out;
-(* mark_debug = "true" *)output wire [0 : 0] gtpowergood_out;
+output wire [0 : 0] gtpowergood_out;
output wire [0 : 0] rxbyteisaligned_out;
output wire [0 : 0] rxbyterealign_out;
output wire [0 : 0] rxcommadet_out;
@@ -192,8 +192,8 @@ output wire [15 : 0] rxctrl0_out;
output wire [15 : 0] rxctrl1_out;
output wire [7 : 0] rxctrl2_out;
output wire [7 : 0] rxctrl3_out;
-(* mark_debug = "true" *)output wire [0 : 0] rxpmaresetdone_out;
-(* mark_debug = "true" *)output wire [0 : 0] txpmaresetdone_out;
+output wire [0 : 0] rxpmaresetdone_out;
+output wire [0 : 0] txpmaresetdone_out;
gtwizard_ultrascale_2_gtwizard_top #(
.C_CHANNEL_ENABLE(192'B000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc
index 326bb3ae1ea8c27c01659b93e05126e11c359a0c..c3d8aaa20fc9e76ba7aec16853c4e5d63c2f3180 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2.xdc
@@ -87,6 +87,8 @@ set_case_analysis 1 [get_pins -filter {REF_PIN_NAME=~*Q} -of_objects [get_ce
set_property CLK_COR_MIN_LAT 32 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[0].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
create_waiver -internal -quiet -user gtwizard_ultrascale -tags 1025417 -type METHODOLOGY -id TIMING-3 -description "added waiver for CPLL CAL local BUFG_GT usecase" -scope \
-objects [get_pins -filter {REF_PIN_NAME=~*O} -of_objects [get_cells -hierarchical -filter {NAME =~ *gen_cpll_cal_inst[*].*bufg_gt_*xoutclkmon_inst}]]
+create_waiver -internal -quiet -type CDC -id {CDC-11} -user gtwizard_ultrascale -tags "1074717" -description "CDC-11 waiver for CPLL Calibration logic" -scope -from [get_pins -quiet -filter {REF_PIN_NAME=~*C} -of_objects [get_cells -hierarchical -filter {NAME =~*OUTCLK_FREQ_COUNTER/state_reg[0]}]] -to [get_pins -quiet -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~*OUTCLK_FREQ_COUNTER/reset_synchronizer_testclk_rst_inst/rst_in_meta_reg*}]]
+create_waiver -internal -quiet -type CDC -id {CDC-11} -user gtwizard_ultrascale -tags "1074717" -description "CDC-11 waiver for CPLL Calibration logic" -scope -from [get_pins -quiet -filter {REF_PIN_NAME=~*C} -of_objects [get_cells -hierarchical -filter {NAME =~*OUTCLK_FREQ_COUNTER/state_reg[0]}]] -to [get_pins -quiet -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~*OUTCLK_FREQ_COUNTER/tstclk_rst_dly1_reg*}]]
# False path constraints
# ----------------------------------------------------------------------------------------------------------------------
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
index e63118e5d6ec082a62fdf1a2471dcf304935db45..ce9fe9e5ab1bcb60730e9e50581f5e21976edee9 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
@@ -403,7 +403,7 @@ module gtwizard_ultrascale_2_gthe4_channel_wrapper #(
-gtwizard_ultrascale_v1_7_7_gthe4_channel #(
+gtwizard_ultrascale_v1_7_14_gthe4_channel #(
.GTHE4_CHANNEL_ACJTAG_DEBUG_MODE (1'b0),
.GTHE4_CHANNEL_ACJTAG_MODE (1'b0),
.GTHE4_CHANNEL_ACJTAG_RESET (1'b0),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
index d8538e225b3ab10d6b7b7736ae8cef307f5c605a..670297531183fe99a0366ab57b652e8cfd1f28cb 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_gthe4.v
@@ -1149,8 +1149,8 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
genvar cm;
for (cm = 0; cm < `gtwizard_ultrascale_2_gtwizard_gthe4_MAX_NUM_COMMONS; cm = cm + 1) begin : gen_common_container
if (P_COMMON_ENABLE[cm] == 1'b1) begin : gen_enabled_common
-
- /* gtwizard_ultrascale_2_gthe4_common_wrapper gthe4_common_wrapper_inst (
+/*
+ gtwizard_ultrascale_2_gthe4_common_wrapper gthe4_common_wrapper_inst (
.GTHE4_COMMON_BGBYPASSB (bgbypassb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
.GTHE4_COMMON_BGMONITORENB (bgmonitorenb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
.GTHE4_COMMON_BGPDB (bgpdb_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]),
@@ -1238,8 +1238,8 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
.GTHE4_COMMON_SDM1TESTDATA (sdm1testdata_int [f_ub_cm(15,(4*cm)+3) : f_lb_cm(15,4*cm)]),
.GTHE4_COMMON_TCONGPO (tcongpo_int [f_ub_cm(10,(4*cm)+3) : f_lb_cm(10,4*cm)]),
.GTHE4_COMMON_TCONRSVDOUT0 (tconrsvdout0_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)])
- );*/
-
+ );
+*/
end
end
@@ -2346,7 +2346,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
// within this inactive generate block for proper HDL fileset hierarchy elaboration
if (0) begin : gen_cpll_cal
- gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal_inst (
+ gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_inst (
.TXOUTCLK_PERIOD_IN (18'b0),
.WAIT_DEASSERT_CPLLPD_IN (16'b0),
.CNT_TOL_IN (18'b0),
@@ -2399,7 +2399,6 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
// Use local parameters and declare both debug and connectivity wires for use with the CPLL calibration block
wire [15:0] p_cpll_cal_freq_count_window_int = P_CPLL_CAL_FREQ_COUNT_WINDOW;
wire [17:0] p_cpll_cal_txoutclk_period_int = P_CPLL_CAL_TXOUTCLK_PERIOD;
- wire [15:0] p_cpll_cal_wait_deassert_cpllpd_int = P_CPLL_CAL_WAIT_DEASSERT_CPLLPD;
wire [17:0] p_cpll_cal_txoutclk_period_div100_int = P_CPLL_CAL_TXOUTCLK_PERIOD_DIV100;
wire [ `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH -1:0] cpll_cal_fail_int;
@@ -2478,7 +2477,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign drpwe_cpll_cal_int[cal] = drpwe_int[cal];
end
else begin: gen_inst_cpll_cal
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal #(
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal #(
.C_SIM_CPLL_CAL_BYPASS(
//pragma translate_off
C_SIM_CPLL_CAL_BYPASS ||
@@ -2490,9 +2489,8 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
.C_RX_PLL_TYPE(C_RX_PLL_TYPE),
.C_TX_PLL_TYPE(C_TX_PLL_TYPE),
.C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
- ) gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_inst (
+ ) gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_inst (
.TXOUTCLK_PERIOD_IN (cpll_cal_txoutclk_period_int[(18*cal)+17:18*cal]),
- .WAIT_DEASSERT_CPLLPD_IN (p_cpll_cal_wait_deassert_cpllpd_int),
.CNT_TOL_IN (cpll_cal_cnt_tol_int[(18*cal)+17:18*cal]),
.FREQ_COUNT_WINDOW_IN (p_cpll_cal_freq_count_window_int),
.RESET_IN (cpll_cal_reset_int[cal]),
@@ -2595,85 +2593,84 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign drpen_ch_int = drpen_int;
assign drpwe_ch_int = drpwe_int;
end
-//GD if (0) begin : gen_cpll_cal_gtye4
-//GD
-//GD gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal #(
-//GD .C_SIM_CPLL_CAL_BYPASS(
-//GD //pragma translate_off
-//GD C_SIM_CPLL_CAL_BYPASS ||
-//GD //pragma translate_on
-//GD 1'b0
-//GD ),
-//GD .C_PCIE_ENABLE(C_PCIE_ENABLE),
-//GD .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
-//GD .C_RX_PLL_TYPE(C_RX_PLL_TYPE),
-//GD .C_TX_PLL_TYPE(C_TX_PLL_TYPE),
-//GD .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
-//GD ) gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst (
-//GD .TXOUTCLK_PERIOD_IN (18'b0),
-//GD .WAIT_DEASSERT_CPLLPD_IN (16'b0),
-//GD .CNT_TOL_IN (18'b0),
-//GD .FREQ_COUNT_WINDOW_IN (16'b0),
-//GD .RESET_IN (1'b0),
-//GD .CLK_IN (1'b0),
-//GD .DRPRST_IN (1'b0),
-//GD .USER_TXOUTCLK_BUFG_CE_IN (1'b0),
-//GD .USER_TXOUTCLK_BUFG_CLR_IN (1'b0),
-//GD .USER_TXPROGDIVRESET_IN (1'b0),
-//GD .GTYE4_RXOUTCLK_IN (1'b0),
-//GD .GTYE4_RXPMARESETDONE_IN (1'b0),
-//GD .GTYE4_RXPRGDIVRESETDONE_IN (1'b0),
-//GD .USER_GTRXRESET_IN (1'b0),
-//GD .USER_RXCDRHOLD_IN (1'b0),
-//GD .USER_RXOUTCLK_BUFG_CE_IN (1'b0),
-//GD .USER_RXOUTCLK_BUFG_CLR_IN (1'b0),
-//GD .USER_RXPMARESET_IN (1'b0),
-//GD .USER_RXPROGDIVRESET_IN (1'b0),
-//GD .USER_RXPLLCLKSEL (2'b00),
-//GD .USER_TXPLLCLKSEL (2'b00),
-//GD .USER_RXOUTCLKSEL_IN (3'b010),
-//GD .GTYE4_GTRXRESET_OUT (),
-//GD .GTYE4_RXCDRHOLD_OUT (),
-//GD .GTYE4_RXPMARESET_OUT (),
-//GD .GTYE4_RXPROGDIVRESET_OUT (),
-//GD .USER_RXPMARESETDONE_OUT (),
-//GD .USER_RXPRGDIVRESETDONE_OUT (),
-//GD .GTYE4_RXOUTCLKSEL_OUT (),
-//GD .USER_TXPRGDIVRESETDONE_OUT (),
-//GD .USER_TXOUTCLKSEL_IN (3'b0),
-//GD .USER_CPLLLOCK_OUT (),
-//GD .USER_CHANNEL_DRPADDR_IN (9'b0),
-//GD .USER_CHANNEL_DRPDI_IN (16'b0),
-//GD .USER_CHANNEL_DRPEN_IN (1'b0),
-//GD .USER_CHANNEL_DRPWE_IN (1'b0),
-//GD .USER_CHANNEL_DRPRDY_OUT (),
-//GD .USER_CHANNEL_DRPDO_OUT (),
-//GD .CPLL_CAL_FAIL (),
-//GD .CPLL_CAL_DONE (),
-//GD .DEBUG_OUT (),
-//GD .CAL_FREQ_CNT (),
-//GD .REPEAT_RESET_LIMIT (4'd15),
-//GD .GTYE4_TXOUTCLK_IN (1'b0),
-//GD .GTYE4_CPLLLOCK_IN (1'b0),
-//GD .GTYE4_CPLLRESET_OUT (),
-//GD .GTYE4_CPLLPD_OUT (),
-//GD .GTYE4_TXPROGDIVRESET_OUT (),
-//GD .GTYE4_TXOUTCLKSEL_OUT (),
-//GD .GTYE4_TXPRGDIVRESETDONE_IN (1'b0),
-//GD .GTYE4_CHANNEL_DRPADDR_OUT (),
-//GD .GTYE4_CHANNEL_DRPDI_OUT (),
-//GD .GTYE4_CHANNEL_DRPEN_OUT (),
-//GD .GTYE4_CHANNEL_DRPWE_OUT (),
-//GD .GTYE4_CHANNEL_DRPRDY_IN (1'b0),
-//GD .GTYE4_CHANNEL_DRPDO_IN (16'b0)
-//GD );
-//GD
-//GD end
+ if (0) begin : gen_cpll_cal_gtye4
+/*
+ gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal #(
+ .C_SIM_CPLL_CAL_BYPASS(
+ //pragma translate_off
+ C_SIM_CPLL_CAL_BYPASS ||
+ //pragma translate_on
+ 1'b0
+ ),
+ .C_PCIE_ENABLE(C_PCIE_ENABLE),
+ .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY),
+ .C_RX_PLL_TYPE(C_RX_PLL_TYPE),
+ .C_TX_PLL_TYPE(C_TX_PLL_TYPE),
+ .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ)
+ ) gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_inst (
+ .TXOUTCLK_PERIOD_IN (18'b0),
+ .CNT_TOL_IN (18'b0),
+ .FREQ_COUNT_WINDOW_IN (16'b0),
+ .RESET_IN (1'b0),
+ .CLK_IN (1'b0),
+ .DRPRST_IN (1'b0),
+ .USER_TXOUTCLK_BUFG_CE_IN (1'b0),
+ .USER_TXOUTCLK_BUFG_CLR_IN (1'b0),
+ .USER_TXPROGDIVRESET_IN (1'b0),
+ .GTYE4_RXOUTCLK_IN (1'b0),
+ .GTYE4_RXPMARESETDONE_IN (1'b0),
+ .GTYE4_RXPRGDIVRESETDONE_IN (1'b0),
+ .USER_GTRXRESET_IN (1'b0),
+ .USER_RXCDRHOLD_IN (1'b0),
+ .USER_RXOUTCLK_BUFG_CE_IN (1'b0),
+ .USER_RXOUTCLK_BUFG_CLR_IN (1'b0),
+ .USER_RXPMARESET_IN (1'b0),
+ .USER_RXPROGDIVRESET_IN (1'b0),
+ .USER_RXPLLCLKSEL (2'b00),
+ .USER_TXPLLCLKSEL (2'b00),
+ .USER_RXOUTCLKSEL_IN (3'b010),
+ .GTYE4_GTRXRESET_OUT (),
+ .GTYE4_RXCDRHOLD_OUT (),
+ .GTYE4_RXPMARESET_OUT (),
+ .GTYE4_RXPROGDIVRESET_OUT (),
+ .USER_RXPMARESETDONE_OUT (),
+ .USER_RXPRGDIVRESETDONE_OUT (),
+ .GTYE4_RXOUTCLKSEL_OUT (),
+ .USER_TXPRGDIVRESETDONE_OUT (),
+ .USER_TXOUTCLKSEL_IN (3'b0),
+ .USER_CPLLLOCK_OUT (),
+ .USER_CHANNEL_DRPADDR_IN (9'b0),
+ .USER_CHANNEL_DRPDI_IN (16'b0),
+ .USER_CHANNEL_DRPEN_IN (1'b0),
+ .USER_CHANNEL_DRPWE_IN (1'b0),
+ .USER_CHANNEL_DRPRDY_OUT (),
+ .USER_CHANNEL_DRPDO_OUT (),
+ .CPLL_CAL_FAIL (),
+ .CPLL_CAL_DONE (),
+ .DEBUG_OUT (),
+ .CAL_FREQ_CNT (),
+ .REPEAT_RESET_LIMIT (4'd15),
+ .GTYE4_TXOUTCLK_IN (1'b0),
+ .GTYE4_CPLLLOCK_IN (1'b0),
+ .GTYE4_CPLLRESET_OUT (),
+ .GTYE4_CPLLPD_OUT (),
+ .GTYE4_TXPROGDIVRESET_OUT (),
+ .GTYE4_TXOUTCLKSEL_OUT (),
+ .GTYE4_TXPRGDIVRESETDONE_IN (1'b0),
+ .GTYE4_CHANNEL_DRPADDR_OUT (),
+ .GTYE4_CHANNEL_DRPDI_OUT (),
+ .GTYE4_CHANNEL_DRPEN_OUT (),
+ .GTYE4_CHANNEL_DRPWE_OUT (),
+ .GTYE4_CHANNEL_DRPRDY_IN (1'b0),
+ .GTYE4_CHANNEL_DRPDO_IN (16'b0)
+ );
+*/
+ end
genvar pwrgood_delay;
for (pwrgood_delay = 0; pwrgood_delay < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; pwrgood_delay = pwrgood_delay + 1) begin : gen_pwrgood_delay_inst
- gtwizard_ultrascale_v1_7_7_gthe4_delay_powergood #(
- .C_USER_GTPOWERGOOD_DELAY_EN ( C_USER_GTPOWERGOOD_DELAY_EN ),
+ gtwizard_ultrascale_v1_7_14_gthe4_delay_powergood #(
+ .C_USER_GTPOWERGOOD_DELAY_EN (C_USER_GTPOWERGOOD_DELAY_EN ),
.C_PCIE_ENABLE (C_PCIE_ENABLE )
) delay_powergood_inst (
.GT_GTPOWERGOOD (gtpowergood_int[pwrgood_delay]),
@@ -2761,7 +2758,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
end
// Instantiate a single instance of the transmitter user clocking network helper block
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
.P_CONTENTS (C_TX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_TX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
@@ -2813,7 +2810,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign gtwiz_userclk_tx_reset_int[gi_hb_txclk] = gtwiz_userclk_rx_reset_in[gi_hb_txclk];
end
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
.P_CONTENTS (C_TX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_TX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
@@ -2897,7 +2894,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
end
// Instantiate a single instance of the receiver user clocking network helper block
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
.P_CONTENTS (C_RX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_RX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
@@ -2951,7 +2948,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign gtwiz_userclk_rx_reset_int[gi_hb_rxclk] = gtwiz_userclk_tx_reset_in;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
.P_CONTENTS (C_RX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_RX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
@@ -3021,7 +3018,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign gtwiz_buffbypass_tx_resetdone_int = >wiz_reset_tx_done_out;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
.P_BUFFER_BYPASS_MODE (C_TX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS),
.P_MASTER_CHANNEL_POINTER (P_TX_MASTER_CH_PACKED_IDX)
@@ -3076,7 +3073,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
genvar gi_hb_txbb;
for (gi_hb_txbb = 0; gi_hb_txbb < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; gi_hb_txbb = gi_hb_txbb + 1) begin : gen_gtwiz_buffbypass_tx
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
.P_BUFFER_BYPASS_MODE (C_TX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (1),
.P_MASTER_CHANNEL_POINTER (0)
@@ -3175,7 +3172,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
assign gtwiz_buffbypass_rx_resetdone_int = >wiz_reset_rx_done_out;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
.P_BUFFER_BYPASS_MODE (C_RX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS),
.P_MASTER_CHANNEL_POINTER (P_RX_MASTER_CH_PACKED_IDX)
@@ -3225,7 +3222,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
genvar gi_hb_rxbb;
for (gi_hb_rxbb = 0; gi_hb_rxbb < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; gi_hb_rxbb = gi_hb_rxbb + 1) begin : gen_gtwiz_buffbypass_rx
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
.P_BUFFER_BYPASS_MODE (C_RX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (1),
.P_MASTER_CHANNEL_POINTER (0)
@@ -3324,7 +3321,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
genvar gi_ch_rxclk;
for (gi_ch_rxclk = 0; gi_ch_rxclk < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; gi_ch_rxclk = gi_ch_rxclk + 1) begin : gen_ch_rxclk
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_userclk_rx_active_out[gi_ch_rxclk]),
.o_out (gtwiz_userclk_rx_active_sync[gi_ch_rxclk])
@@ -3369,12 +3366,12 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
wire [`gtwizard_ultrascale_2_gtwizard_gthe4_N_CH-1:0] rxresetdone_sync;
genvar gi_ch_xrd;
for (gi_ch_xrd = 0; gi_ch_xrd < `gtwizard_ultrascale_2_gtwizard_gthe4_N_CH; gi_ch_xrd = gi_ch_xrd + 1) begin : gen_ch_xrd
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txresetdone_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (txresetdone_int[gi_ch_xrd]),
.o_out (txresetdone_sync[gi_ch_xrd])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxresetdone_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (rxresetdone_int[gi_ch_xrd]),
.o_out (rxresetdone_sync[gi_ch_xrd])
@@ -3413,7 +3410,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
end
// Instantiate the single reset controller
- gtwizard_ultrascale_v1_7_7_gtwiz_reset #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_reset #(
.P_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY),
.P_USE_CPLL_CAL (0),
.P_TX_PLL_TYPE (C_TX_PLL_TYPE),
@@ -3604,7 +3601,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
endcase
// Instantiate a reset controller per channel
- gtwizard_ultrascale_v1_7_7_gtwiz_reset #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_reset #(
.P_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY),
.P_USE_CPLL_CAL (0),
.P_TX_PLL_TYPE (C_TX_PLL_TYPE),
@@ -3778,7 +3775,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
wire [(C_TOTAL_NUM_CHANNELS* 16)-1:0] gtwiz_userdata_tx_txctrl0_int;
wire [(C_TOTAL_NUM_CHANNELS* 16)-1:0] gtwiz_userdata_tx_txctrl1_int;
- gtwizard_ultrascale_v1_7_7_gtwiz_userdata_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userdata_tx #(
.P_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH),
.P_TX_DATA_ENCODING (C_TX_DATA_ENCODING),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS)
@@ -3824,7 +3821,7 @@ module gtwizard_ultrascale_2_gtwizard_gthe4 #(
(C_LOCATE_USER_DATA_WIDTH_SIZING == `gtwizard_ultrascale_2_gtwizard_gthe4_LOCATE_USER_DATA_WIDTH_SIZING__CORE))
begin : gen_rx_userdata_internal
- gtwizard_ultrascale_v1_7_7_gtwiz_userdata_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userdata_rx #(
.P_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH),
.P_RX_DATA_DECODING (C_RX_DATA_DECODING),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
index 81f6095618479055cd9576cc2868a7ca13204ddb..b1db996ea5185498084d7cfbab472f10568cc192 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_2_gtwizard_top.v
@@ -1273,1044 +1273,1584 @@ module gtwizard_ultrascale_2_gtwizard_top #(
// ================================================================================================================
generate if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTHE3) begin : gen_gtwizard_gthe3_top
+/*
+ // Generate GTHE3-type Transceivers Wizard submodule
+ gtwizard_ultrascale_2_gtwizard_gthe3 #(
+ .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
+ .C_PCIE_ENABLE (C_PCIE_ENABLE ),
+ .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
+ .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
+ .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
+ .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
+ .C_GT_REV (C_GT_REV ),
+ .C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
+ .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
+ .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
+ .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
+ .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
+ .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
+ .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
+ .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
+ .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
+ .C_RX_ENABLE (C_RX_ENABLE ),
+ .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
+ .C_RX_LINE_RATE (C_RX_LINE_RATE ),
+ .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
+ .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
+ .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
+ .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
+ .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
+ .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
+ .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
+ .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
+ .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
+ .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
+ .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
+ .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
+ .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
+ .C_TX_ENABLE (C_TX_ENABLE ),
+ .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
+ .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
+ .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
+ .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
+ .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
+ .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
+ .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
+ ) gtwizard_ultrascale_2_gtwizard_gthe3_inst (
+ .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
+ .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
+ .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
+ .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
+ .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
+ .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
+ .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
+ .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
+ .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
+ .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
+ .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
+ .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
+ .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
+ .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
+ .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
+ .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
+ .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
+ .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
+ .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
+ .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
+ .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
+ .gtwiz_reset_all_in (gtwiz_reset_all_in ),
+ .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in ),
+ .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
+ .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in ),
+ .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
+ .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
+ .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
+ .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
+ .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
+ .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
+ .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
+ .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
+ .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
+ .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
+ .gtwiz_gthe3_cpll_cal_txoutclk_period_in (gtwiz_gthe3_cpll_cal_txoutclk_period_in),
+ .gtwiz_gthe3_cpll_cal_cnt_tol_in (gtwiz_gthe3_cpll_cal_cnt_tol_in ),
+ .gtwiz_gthe3_cpll_cal_bufg_ce_in (gtwiz_gthe3_cpll_cal_bufg_ce_in ),
+ .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
+ .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
+ .bgbypassb_in (bgbypassb_in ),
+ .bgmonitorenb_in (bgmonitorenb_in ),
+ .bgpdb_in (bgpdb_in ),
+ .bgrcalovrd_in (bgrcalovrd_in ),
+ .bgrcalovrdenb_in (bgrcalovrdenb_in ),
+ .drpaddr_common_in (drpaddr_common_in ),
+ .drpclk_common_in (drpclk_common_in ),
+ .drpdi_common_in (drpdi_common_in ),
+ .drpen_common_in (drpen_common_in ),
+ .drpwe_common_in (drpwe_common_in ),
+ .gtgrefclk0_in (gtgrefclk0_in ),
+ .gtgrefclk1_in (gtgrefclk1_in ),
+ .gtnorthrefclk00_in (gtnorthrefclk00_in ),
+ .gtnorthrefclk01_in (gtnorthrefclk01_in ),
+ .gtnorthrefclk10_in (gtnorthrefclk10_in ),
+ .gtnorthrefclk11_in (gtnorthrefclk11_in ),
+ .gtrefclk00_in (gtrefclk00_in ),
+ .gtrefclk01_in (gtrefclk01_in ),
+ .gtrefclk10_in (gtrefclk10_in ),
+ .gtrefclk11_in (gtrefclk11_in ),
+ .gtsouthrefclk00_in (gtsouthrefclk00_in ),
+ .gtsouthrefclk01_in (gtsouthrefclk01_in ),
+ .gtsouthrefclk10_in (gtsouthrefclk10_in ),
+ .gtsouthrefclk11_in (gtsouthrefclk11_in ),
+ .pmarsvd0_in (pmarsvd0_in ),
+ .pmarsvd1_in (pmarsvd1_in ),
+ .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
+ .qpll0clkrsvd1_in (qpll0clkrsvd1_in ),
+ .qpll0lockdetclk_in (qpll0lockdetclk_in ),
+ .qpll0locken_in (qpll0locken_in ),
+ .qpll0pd_in (qpll0pd_in ),
+ .qpll0refclksel_in (qpll0refclksel_in ),
+ .qpll0reset_in (qpll0reset_in ),
+ .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
+ .qpll1clkrsvd1_in (qpll1clkrsvd1_in ),
+ .qpll1lockdetclk_in (qpll1lockdetclk_in ),
+ .qpll1locken_in (qpll1locken_in ),
+ .qpll1pd_in (qpll1pd_in ),
+ .qpll1refclksel_in (qpll1refclksel_in ),
+ .qpll1reset_in (qpll1reset_in ),
+ .qpllrsvd1_in (qpllrsvd1_in ),
+ .qpllrsvd2_in (qpllrsvd2_in ),
+ .qpllrsvd3_in (qpllrsvd3_in ),
+ .qpllrsvd4_in (qpllrsvd4_in ),
+ .rcalenb_in (rcalenb_in ),
+ .drpdo_common_out (drpdo_common_out ),
+ .drprdy_common_out (drprdy_common_out ),
+ .pmarsvdout0_out (pmarsvdout0_out ),
+ .pmarsvdout1_out (pmarsvdout1_out ),
+ .qpll0fbclklost_out (qpll0fbclklost_out ),
+ .qpll0lock_out (qpll0lock_out ),
+ .qpll0outclk_out (qpll0outclk_out ),
+ .qpll0outrefclk_out (qpll0outrefclk_out ),
+ .qpll0refclklost_out (qpll0refclklost_out ),
+ .qpll1fbclklost_out (qpll1fbclklost_out ),
+ .qpll1lock_out (qpll1lock_out ),
+ .qpll1outclk_out (qpll1outclk_out ),
+ .qpll1outrefclk_out (qpll1outrefclk_out ),
+ .qpll1refclklost_out (qpll1refclklost_out ),
+ .qplldmonitor0_out (qplldmonitor0_out ),
+ .qplldmonitor1_out (qplldmonitor1_out ),
+ .refclkoutmonitor0_out (refclkoutmonitor0_out ),
+ .refclkoutmonitor1_out (refclkoutmonitor1_out ),
+ .rxrecclk0_sel_out (rxrecclk0_sel_out ),
+ .rxrecclk1_sel_out (rxrecclk1_sel_out ),
+ .cfgreset_in (cfgreset_in ),
+ .clkrsvd0_in (clkrsvd0_in ),
+ .clkrsvd1_in (clkrsvd1_in ),
+ .cplllockdetclk_in (cplllockdetclk_in ),
+ .cplllocken_in (cplllocken_in ),
+ .cpllpd_in (cpllpd_in ),
+ .cpllrefclksel_in (cpllrefclksel_in ),
+ .cpllreset_in (cpllreset_in ),
+ .dmonfiforeset_in (dmonfiforeset_in ),
+ .dmonitorclk_in (dmonitorclk_in ),
+ .drpaddr_in (drpaddr_in ),
+ .drpclk_in (drpclk_in ),
+ .drpdi_in (drpdi_in ),
+ .drpen_in (drpen_in ),
+ .drpwe_in (drpwe_in ),
+ .evoddphicaldone_in (evoddphicaldone_in ),
+ .evoddphicalstart_in (evoddphicalstart_in ),
+ .evoddphidrden_in (evoddphidrden_in ),
+ .evoddphidwren_in (evoddphidwren_in ),
+ .evoddphixrden_in (evoddphixrden_in ),
+ .evoddphixwren_in (evoddphixwren_in ),
+ .eyescanmode_in (eyescanmode_in ),
+ .eyescanreset_in (eyescanreset_in ),
+ .eyescantrigger_in (eyescantrigger_in ),
+ .gtgrefclk_in (gtgrefclk_in ),
+ .gthrxn_in (gthrxn_in ),
+ .gthrxp_in (gthrxp_in ),
+ .gtnorthrefclk0_in (gtnorthrefclk0_in ),
+ .gtnorthrefclk1_in (gtnorthrefclk1_in ),
+ .gtrefclk0_in (gtrefclk0_in ),
+ .gtrefclk1_in (gtrefclk1_in ),
+ .gtresetsel_in (gtresetsel_in ),
+ .gtrsvd_in (gtrsvd_in ),
+ .gtrxreset_in (gtrxreset_in ),
+ .gtsouthrefclk0_in (gtsouthrefclk0_in ),
+ .gtsouthrefclk1_in (gtsouthrefclk1_in ),
+ .gttxreset_in (gttxreset_in ),
+ .loopback_in (loopback_in ),
+ .lpbkrxtxseren_in (lpbkrxtxseren_in ),
+ .lpbktxrxseren_in (lpbktxrxseren_in ),
+ .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
+ .pcierstidle_in (pcierstidle_in ),
+ .pciersttxsyncstart_in (pciersttxsyncstart_in ),
+ .pcieuserratedone_in (pcieuserratedone_in ),
+ .pcsrsvdin_in (pcsrsvdin_in ),
+ .pcsrsvdin2_in (pcsrsvdin2_in ),
+ .pmarsvdin_in (pmarsvdin_in ),
+ .qpll0clk_in (qpll0clk_in ),
+ .qpll0refclk_in (qpll0refclk_in ),
+ .qpll1clk_in (qpll1clk_in ),
+ .qpll1refclk_in (qpll1refclk_in ),
+ .resetovrd_in (resetovrd_in ),
+ .rstclkentx_in (rstclkentx_in ),
+ .rx8b10ben_in (rx8b10ben_in ),
+ .rxbufreset_in (rxbufreset_in ),
+ .rxcdrfreqreset_in (rxcdrfreqreset_in ),
+ .rxcdrhold_in (rxcdrhold_in ),
+ .rxcdrovrden_in (rxcdrovrden_in ),
+ .rxcdrreset_in (rxcdrreset_in ),
+ .rxcdrresetrsv_in (rxcdrresetrsv_in ),
+ .rxchbonden_in (rxchbonden_in ),
+ .rxchbondi_in (rxchbondi_in ),
+ .rxchbondlevel_in (rxchbondlevel_in ),
+ .rxchbondmaster_in (rxchbondmaster_in ),
+ .rxchbondslave_in (rxchbondslave_in ),
+ .rxcommadeten_in (rxcommadeten_in ),
+ .rxdfeagcctrl_in (rxdfeagcctrl_in ),
+ .rxdfeagchold_in (rxdfeagchold_in ),
+ .rxdfeagcovrden_in (rxdfeagcovrden_in ),
+ .rxdfelfhold_in (rxdfelfhold_in ),
+ .rxdfelfovrden_in (rxdfelfovrden_in ),
+ .rxdfelpmreset_in (rxdfelpmreset_in ),
+ .rxdfetap10hold_in (rxdfetap10hold_in ),
+ .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
+ .rxdfetap11hold_in (rxdfetap11hold_in ),
+ .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
+ .rxdfetap12hold_in (rxdfetap12hold_in ),
+ .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
+ .rxdfetap13hold_in (rxdfetap13hold_in ),
+ .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
+ .rxdfetap14hold_in (rxdfetap14hold_in ),
+ .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
+ .rxdfetap15hold_in (rxdfetap15hold_in ),
+ .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
+ .rxdfetap2hold_in (rxdfetap2hold_in ),
+ .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
+ .rxdfetap3hold_in (rxdfetap3hold_in ),
+ .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
+ .rxdfetap4hold_in (rxdfetap4hold_in ),
+ .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
+ .rxdfetap5hold_in (rxdfetap5hold_in ),
+ .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
+ .rxdfetap6hold_in (rxdfetap6hold_in ),
+ .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
+ .rxdfetap7hold_in (rxdfetap7hold_in ),
+ .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
+ .rxdfetap8hold_in (rxdfetap8hold_in ),
+ .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
+ .rxdfetap9hold_in (rxdfetap9hold_in ),
+ .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
+ .rxdfeuthold_in (rxdfeuthold_in ),
+ .rxdfeutovrden_in (rxdfeutovrden_in ),
+ .rxdfevphold_in (rxdfevphold_in ),
+ .rxdfevpovrden_in (rxdfevpovrden_in ),
+ .rxdfevsen_in (rxdfevsen_in ),
+ .rxdfexyden_in (rxdfexyden_in ),
+ .rxdlybypass_in (rxdlybypass_in ),
+ .rxdlyen_in (rxdlyen_in ),
+ .rxdlyovrden_in (rxdlyovrden_in ),
+ .rxdlysreset_in (rxdlysreset_in ),
+ .rxelecidlemode_in (rxelecidlemode_in ),
+ .rxgearboxslip_in (rxgearboxslip_in ),
+ .rxlatclk_in (rxlatclk_in ),
+ .rxlpmen_in (rxlpmen_in ),
+ .rxlpmgchold_in (rxlpmgchold_in ),
+ .rxlpmgcovrden_in (rxlpmgcovrden_in ),
+ .rxlpmhfhold_in (rxlpmhfhold_in ),
+ .rxlpmhfovrden_in (rxlpmhfovrden_in ),
+ .rxlpmlfhold_in (rxlpmlfhold_in ),
+ .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
+ .rxlpmoshold_in (rxlpmoshold_in ),
+ .rxlpmosovrden_in (rxlpmosovrden_in ),
+ .rxmcommaalignen_in (rxmcommaalignen_in ),
+ .rxmonitorsel_in (rxmonitorsel_in ),
+ .rxoobreset_in (rxoobreset_in ),
+ .rxoscalreset_in (rxoscalreset_in ),
+ .rxoshold_in (rxoshold_in ),
+ .rxosintcfg_in (rxosintcfg_in ),
+ .rxosinten_in (rxosinten_in ),
+ .rxosinthold_in (rxosinthold_in ),
+ .rxosintovrden_in (rxosintovrden_in ),
+ .rxosintstrobe_in (rxosintstrobe_in ),
+ .rxosinttestovrden_in (rxosinttestovrden_in ),
+ .rxosovrden_in (rxosovrden_in ),
+ .rxoutclksel_in (rxoutclksel_in ),
+ .rxpcommaalignen_in (rxpcommaalignen_in ),
+ .rxpcsreset_in (rxpcsreset_in ),
+ .rxpd_in (rxpd_in ),
+ .rxphalign_in (rxphalign_in ),
+ .rxphalignen_in (rxphalignen_in ),
+ .rxphdlypd_in (rxphdlypd_in ),
+ .rxphdlyreset_in (rxphdlyreset_in ),
+ .rxphovrden_in (rxphovrden_in ),
+ .rxpllclksel_in (rxpllclksel_in ),
+ .rxpmareset_in (rxpmareset_in ),
+ .rxpolarity_in (rxpolarity_in ),
+ .rxprbscntreset_in (rxprbscntreset_in ),
+ .rxprbssel_in (rxprbssel_in ),
+ .rxprogdivreset_in (rxprogdivreset_in ),
+ .rxqpien_in (rxqpien_in ),
+ .rxrate_in (rxrate_in ),
+ .rxratemode_in (rxratemode_in ),
+ .rxslide_in (rxslide_in ),
+ .rxslipoutclk_in (rxslipoutclk_in ),
+ .rxslippma_in (rxslippma_in ),
+ .rxsyncallin_in (rxsyncallin_in ),
+ .rxsyncin_in (rxsyncin_in ),
+ .rxsyncmode_in (rxsyncmode_in ),
+ .rxsysclksel_in (rxsysclksel_in ),
+ .rxuserrdy_in (rxuserrdy_in ),
+ .rxusrclk_in (rxusrclk_in ),
+ .rxusrclk2_in (rxusrclk2_in ),
+ .sigvalidclk_in (sigvalidclk_in ),
+ .tstin_in (tstin_in ),
+ .tx8b10bbypass_in (tx8b10bbypass_in ),
+ .tx8b10ben_in (tx8b10ben_in ),
+ .txbufdiffctrl_in (txbufdiffctrl_in ),
+ .txcominit_in (txcominit_in ),
+ .txcomsas_in (txcomsas_in ),
+ .txcomwake_in (txcomwake_in ),
+ .txctrl0_in (txctrl0_in ),
+ .txctrl1_in (txctrl1_in ),
+ .txctrl2_in (txctrl2_in ),
+ .txdata_in (txdata_in ),
+ .txdataextendrsvd_in (txdataextendrsvd_in ),
+ .txdeemph_in (txdeemph_in ),
+ .txdetectrx_in (txdetectrx_in ),
+ .txdiffctrl_in (txdiffctrl_in ),
+ .txdiffpd_in (txdiffpd_in ),
+ .txdlybypass_in (txdlybypass_in ),
+ .txdlyen_in (txdlyen_in ),
+ .txdlyhold_in (txdlyhold_in ),
+ .txdlyovrden_in (txdlyovrden_in ),
+ .txdlysreset_in (txdlysreset_in ),
+ .txdlyupdown_in (txdlyupdown_in ),
+ .txelecidle_in (txelecidle_in ),
+ .txheader_in (txheader_in ),
+ .txinhibit_in (txinhibit_in ),
+ .txlatclk_in (txlatclk_in ),
+ .txmaincursor_in (txmaincursor_in ),
+ .txmargin_in (txmargin_in ),
+ .txoutclksel_in (txoutclksel_in ),
+ .txpcsreset_in (txpcsreset_in ),
+ .txpd_in (txpd_in ),
+ .txpdelecidlemode_in (txpdelecidlemode_in ),
+ .txphalign_in (txphalign_in ),
+ .txphalignen_in (txphalignen_in ),
+ .txphdlypd_in (txphdlypd_in ),
+ .txphdlyreset_in (txphdlyreset_in ),
+ .txphdlytstclk_in (txphdlytstclk_in ),
+ .txphinit_in (txphinit_in ),
+ .txphovrden_in (txphovrden_in ),
+ .txpippmen_in (txpippmen_in ),
+ .txpippmovrden_in (txpippmovrden_in ),
+ .txpippmpd_in (txpippmpd_in ),
+ .txpippmsel_in (txpippmsel_in ),
+ .txpippmstepsize_in (txpippmstepsize_in ),
+ .txpisopd_in (txpisopd_in ),
+ .txpllclksel_in (txpllclksel_in ),
+ .txpmareset_in (txpmareset_in ),
+ .txpolarity_in (txpolarity_in ),
+ .txpostcursor_in (txpostcursor_in ),
+ .txpostcursorinv_in (txpostcursorinv_in ),
+ .txprbsforceerr_in (txprbsforceerr_in ),
+ .txprbssel_in (txprbssel_in ),
+ .txprecursor_in (txprecursor_in ),
+ .txprecursorinv_in (txprecursorinv_in ),
+ .txprogdivreset_in (txprogdivreset_in ),
+ .txqpibiasen_in (txqpibiasen_in ),
+ .txqpistrongpdown_in (txqpistrongpdown_in ),
+ .txqpiweakpup_in (txqpiweakpup_in ),
+ .txrate_in (txrate_in ),
+ .txratemode_in (txratemode_in ),
+ .txsequence_in (txsequence_in ),
+ .txswing_in (txswing_in ),
+ .txsyncallin_in (txsyncallin_in ),
+ .txsyncin_in (txsyncin_in ),
+ .txsyncmode_in (txsyncmode_in ),
+ .txsysclksel_in (txsysclksel_in ),
+ .txuserrdy_in (txuserrdy_in ),
+ .txusrclk_in (txusrclk_in ),
+ .txusrclk2_in (txusrclk2_in ),
+ .bufgtce_out (bufgtce_out ),
+ .bufgtcemask_out (bufgtcemask_out ),
+ .bufgtdiv_out (bufgtdiv_out ),
+ .bufgtreset_out (bufgtreset_out ),
+ .bufgtrstmask_out (bufgtrstmask_out ),
+ .cpllfbclklost_out (cpllfbclklost_out ),
+ .cplllock_out (cplllock_out ),
+ .cpllrefclklost_out (cpllrefclklost_out ),
+ .dmonitorout_out (dmonitorout_out ),
+ .drpdo_out (drpdo_out ),
+ .drprdy_out (drprdy_out ),
+ .eyescandataerror_out (eyescandataerror_out ),
+ .gthtxn_out (gthtxn_out ),
+ .gthtxp_out (gthtxp_out ),
+ .gtpowergood_out (gtpowergood_out ),
+ .gtrefclkmonitor_out (gtrefclkmonitor_out ),
+ .pcierategen3_out (pcierategen3_out ),
+ .pcierateidle_out (pcierateidle_out ),
+ .pcierateqpllpd_out (pcierateqpllpd_out ),
+ .pcierateqpllreset_out (pcierateqpllreset_out ),
+ .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
+ .pcieusergen3rdy_out (pcieusergen3rdy_out ),
+ .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
+ .pcieuserratestart_out (pcieuserratestart_out ),
+ .pcsrsvdout_out (pcsrsvdout_out ),
+ .phystatus_out (phystatus_out ),
+ .pinrsrvdas_out (pinrsrvdas_out ),
+ .resetexception_out (resetexception_out ),
+ .rxbufstatus_out (rxbufstatus_out ),
+ .rxbyteisaligned_out (rxbyteisaligned_out ),
+ .rxbyterealign_out (rxbyterealign_out ),
+ .rxcdrlock_out (rxcdrlock_out ),
+ .rxcdrphdone_out (rxcdrphdone_out ),
+ .rxchanbondseq_out (rxchanbondseq_out ),
+ .rxchanisaligned_out (rxchanisaligned_out ),
+ .rxchanrealign_out (rxchanrealign_out ),
+ .rxchbondo_out (rxchbondo_out ),
+ .rxclkcorcnt_out (rxclkcorcnt_out ),
+ .rxcominitdet_out (rxcominitdet_out ),
+ .rxcommadet_out (rxcommadet_out ),
+ .rxcomsasdet_out (rxcomsasdet_out ),
+ .rxcomwakedet_out (rxcomwakedet_out ),
+ .rxctrl0_out (rxctrl0_out ),
+ .rxctrl1_out (rxctrl1_out ),
+ .rxctrl2_out (rxctrl2_out ),
+ .rxctrl3_out (rxctrl3_out ),
+ .rxdata_out (rxdata_out ),
+ .rxdataextendrsvd_out (rxdataextendrsvd_out ),
+ .rxdatavalid_out (rxdatavalid_out ),
+ .rxdlysresetdone_out (rxdlysresetdone_out ),
+ .rxelecidle_out (rxelecidle_out ),
+ .rxheader_out (rxheader_out ),
+ .rxheadervalid_out (rxheadervalid_out ),
+ .rxmonitorout_out (rxmonitorout_out ),
+ .rxosintdone_out (rxosintdone_out ),
+ .rxosintstarted_out (rxosintstarted_out ),
+ .rxosintstrobedone_out (rxosintstrobedone_out ),
+ .rxosintstrobestarted_out (rxosintstrobestarted_out ),
+ .rxoutclk_out (rxoutclk_out ),
+ .rxoutclkfabric_out (rxoutclkfabric_out ),
+ .rxoutclkpcs_out (rxoutclkpcs_out ),
+ .rxphaligndone_out (rxphaligndone_out ),
+ .rxphalignerr_out (rxphalignerr_out ),
+ .rxpmaresetdone_out (rxpmaresetdone_out ),
+ .rxprbserr_out (rxprbserr_out ),
+ .rxprbslocked_out (rxprbslocked_out ),
+ .rxprgdivresetdone_out (rxprgdivresetdone_out ),
+ .rxqpisenn_out (rxqpisenn_out ),
+ .rxqpisenp_out (rxqpisenp_out ),
+ .rxratedone_out (rxratedone_out ),
+ .rxrecclkout_out (rxrecclkout_out ),
+ .rxresetdone_out (rxresetdone_out ),
+ .rxsliderdy_out (rxsliderdy_out ),
+ .rxslipdone_out (rxslipdone_out ),
+ .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
+ .rxslippmardy_out (rxslippmardy_out ),
+ .rxstartofseq_out (rxstartofseq_out ),
+ .rxstatus_out (rxstatus_out ),
+ .rxsyncdone_out (rxsyncdone_out ),
+ .rxsyncout_out (rxsyncout_out ),
+ .rxvalid_out (rxvalid_out ),
+ .txbufstatus_out (txbufstatus_out ),
+ .txcomfinish_out (txcomfinish_out ),
+ .txdlysresetdone_out (txdlysresetdone_out ),
+ .txoutclk_out (txoutclk_out ),
+ .txoutclkfabric_out (txoutclkfabric_out ),
+ .txoutclkpcs_out (txoutclkpcs_out ),
+ .txphaligndone_out (txphaligndone_out ),
+ .txphinitdone_out (txphinitdone_out ),
+ .txpmaresetdone_out (txpmaresetdone_out ),
+ .txprgdivresetdone_out (txprgdivresetdone_out ),
+ .txqpisenn_out (txqpisenn_out ),
+ .txqpisenp_out (txqpisenp_out ),
+ .txratedone_out (txratedone_out ),
+ .txresetdone_out (txresetdone_out ),
+ .txsyncdone_out (txsyncdone_out ),
+ .txsyncout_out (txsyncout_out )
+ );
-// // Generate GTHE3-type Transceivers Wizard submodule
-// gtwizard_ultrascale_2_gtwizard_gthe3 #(
-// .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
-// .C_PCIE_ENABLE (C_PCIE_ENABLE ),
-// .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
-// .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
-// .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
-// .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
-// .C_GT_REV (C_GT_REV ),
-// .C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
-// .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
-// .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
-// .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
-// .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
-// .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
-// .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
-// .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
-// .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
-// .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
-// .C_RX_ENABLE (C_RX_ENABLE ),
-// .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
-// .C_RX_LINE_RATE (C_RX_LINE_RATE ),
-// .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
-// .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
-// .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
-// .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
-// .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
-// .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
-// .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
-// .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
-// .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
-// .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
-// .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
-// .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
-// .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
-// .C_TX_ENABLE (C_TX_ENABLE ),
-// .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
-// .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
-// .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
-// .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
-// .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
-// .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
-// .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
-// ) gtwizard_ultrascale_2_gtwizard_gthe3_inst (
-// .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
-// .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
-// .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
-// .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
-// .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
-// .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
-// .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
-// .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
-// .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
-// .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
-// .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
-// .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
-// .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
-// .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
-// .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
-// .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
-// .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
-// .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
-// .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
-// .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
-// .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
-// .gtwiz_reset_all_in (gtwiz_reset_all_in ),
-// .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in ),
-// .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
-// .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in ),
-// .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
-// .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
-// .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
-// .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
-// .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
-// .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
-// .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
-// .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
-// .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
-// .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
-// .gtwiz_gthe3_cpll_cal_txoutclk_period_in (gtwiz_gthe3_cpll_cal_txoutclk_period_in),
-// .gtwiz_gthe3_cpll_cal_cnt_tol_in (gtwiz_gthe3_cpll_cal_cnt_tol_in ),
-// .gtwiz_gthe3_cpll_cal_bufg_ce_in (gtwiz_gthe3_cpll_cal_bufg_ce_in ),
-// .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
-// .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
-// .bgbypassb_in (bgbypassb_in ),
-// .bgmonitorenb_in (bgmonitorenb_in ),
-// .bgpdb_in (bgpdb_in ),
-// .bgrcalovrd_in (bgrcalovrd_in ),
-// .bgrcalovrdenb_in (bgrcalovrdenb_in ),
-// .drpaddr_common_in (drpaddr_common_in ),
-// .drpclk_common_in (drpclk_common_in ),
-// .drpdi_common_in (drpdi_common_in ),
-// .drpen_common_in (drpen_common_in ),
-// .drpwe_common_in (drpwe_common_in ),
-// .gtgrefclk0_in (gtgrefclk0_in ),
-// .gtgrefclk1_in (gtgrefclk1_in ),
-// .gtnorthrefclk00_in (gtnorthrefclk00_in ),
-// .gtnorthrefclk01_in (gtnorthrefclk01_in ),
-// .gtnorthrefclk10_in (gtnorthrefclk10_in ),
-// .gtnorthrefclk11_in (gtnorthrefclk11_in ),
-// .gtrefclk00_in (gtrefclk00_in ),
-// .gtrefclk01_in (gtrefclk01_in ),
-// .gtrefclk10_in (gtrefclk10_in ),
-// .gtrefclk11_in (gtrefclk11_in ),
-// .gtsouthrefclk00_in (gtsouthrefclk00_in ),
-// .gtsouthrefclk01_in (gtsouthrefclk01_in ),
-// .gtsouthrefclk10_in (gtsouthrefclk10_in ),
-// .gtsouthrefclk11_in (gtsouthrefclk11_in ),
-// .pmarsvd0_in (pmarsvd0_in ),
-// .pmarsvd1_in (pmarsvd1_in ),
-// .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
-// .qpll0clkrsvd1_in (qpll0clkrsvd1_in ),
-// .qpll0lockdetclk_in (qpll0lockdetclk_in ),
-// .qpll0locken_in (qpll0locken_in ),
-// .qpll0pd_in (qpll0pd_in ),
-// .qpll0refclksel_in (qpll0refclksel_in ),
-// .qpll0reset_in (qpll0reset_in ),
-// .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
-// .qpll1clkrsvd1_in (qpll1clkrsvd1_in ),
-// .qpll1lockdetclk_in (qpll1lockdetclk_in ),
-// .qpll1locken_in (qpll1locken_in ),
-// .qpll1pd_in (qpll1pd_in ),
-// .qpll1refclksel_in (qpll1refclksel_in ),
-// .qpll1reset_in (qpll1reset_in ),
-// .qpllrsvd1_in (qpllrsvd1_in ),
-// .qpllrsvd2_in (qpllrsvd2_in ),
-// .qpllrsvd3_in (qpllrsvd3_in ),
-// .qpllrsvd4_in (qpllrsvd4_in ),
-// .rcalenb_in (rcalenb_in ),
-// .drpdo_common_out (drpdo_common_out ),
-// .drprdy_common_out (drprdy_common_out ),
-// .pmarsvdout0_out (pmarsvdout0_out ),
-// .pmarsvdout1_out (pmarsvdout1_out ),
-// .qpll0fbclklost_out (qpll0fbclklost_out ),
-// .qpll0lock_out (qpll0lock_out ),
-// .qpll0outclk_out (qpll0outclk_out ),
-// .qpll0outrefclk_out (qpll0outrefclk_out ),
-// .qpll0refclklost_out (qpll0refclklost_out ),
-// .qpll1fbclklost_out (qpll1fbclklost_out ),
-// .qpll1lock_out (qpll1lock_out ),
-// .qpll1outclk_out (qpll1outclk_out ),
-// .qpll1outrefclk_out (qpll1outrefclk_out ),
-// .qpll1refclklost_out (qpll1refclklost_out ),
-// .qplldmonitor0_out (qplldmonitor0_out ),
-// .qplldmonitor1_out (qplldmonitor1_out ),
-// .refclkoutmonitor0_out (refclkoutmonitor0_out ),
-// .refclkoutmonitor1_out (refclkoutmonitor1_out ),
-// .rxrecclk0_sel_out (rxrecclk0_sel_out ),
-// .rxrecclk1_sel_out (rxrecclk1_sel_out ),
-// .cfgreset_in (cfgreset_in ),
-// .clkrsvd0_in (clkrsvd0_in ),
-// .clkrsvd1_in (clkrsvd1_in ),
-// .cplllockdetclk_in (cplllockdetclk_in ),
-// .cplllocken_in (cplllocken_in ),
-// .cpllpd_in (cpllpd_in ),
-// .cpllrefclksel_in (cpllrefclksel_in ),
-// .cpllreset_in (cpllreset_in ),
-// .dmonfiforeset_in (dmonfiforeset_in ),
-// .dmonitorclk_in (dmonitorclk_in ),
-// .drpaddr_in (drpaddr_in ),
-// .drpclk_in (drpclk_in ),
-// .drpdi_in (drpdi_in ),
-// .drpen_in (drpen_in ),
-// .drpwe_in (drpwe_in ),
-// .evoddphicaldone_in (evoddphicaldone_in ),
-// .evoddphicalstart_in (evoddphicalstart_in ),
-// .evoddphidrden_in (evoddphidrden_in ),
-// .evoddphidwren_in (evoddphidwren_in ),
-// .evoddphixrden_in (evoddphixrden_in ),
-// .evoddphixwren_in (evoddphixwren_in ),
-// .eyescanmode_in (eyescanmode_in ),
-// .eyescanreset_in (eyescanreset_in ),
-// .eyescantrigger_in (eyescantrigger_in ),
-// .gtgrefclk_in (gtgrefclk_in ),
-// .gthrxn_in (gthrxn_in ),
-// .gthrxp_in (gthrxp_in ),
-// .gtnorthrefclk0_in (gtnorthrefclk0_in ),
-// .gtnorthrefclk1_in (gtnorthrefclk1_in ),
-// .gtrefclk0_in (gtrefclk0_in ),
-// .gtrefclk1_in (gtrefclk1_in ),
-// .gtresetsel_in (gtresetsel_in ),
-// .gtrsvd_in (gtrsvd_in ),
-// .gtrxreset_in (gtrxreset_in ),
-// .gtsouthrefclk0_in (gtsouthrefclk0_in ),
-// .gtsouthrefclk1_in (gtsouthrefclk1_in ),
-// .gttxreset_in (gttxreset_in ),
-// .loopback_in (loopback_in ),
-// .lpbkrxtxseren_in (lpbkrxtxseren_in ),
-// .lpbktxrxseren_in (lpbktxrxseren_in ),
-// .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
-// .pcierstidle_in (pcierstidle_in ),
-// .pciersttxsyncstart_in (pciersttxsyncstart_in ),
-// .pcieuserratedone_in (pcieuserratedone_in ),
-// .pcsrsvdin_in (pcsrsvdin_in ),
-// .pcsrsvdin2_in (pcsrsvdin2_in ),
-// .pmarsvdin_in (pmarsvdin_in ),
-// .qpll0clk_in (qpll0clk_in ),
-// .qpll0refclk_in (qpll0refclk_in ),
-// .qpll1clk_in (qpll1clk_in ),
-// .qpll1refclk_in (qpll1refclk_in ),
-// .resetovrd_in (resetovrd_in ),
-// .rstclkentx_in (rstclkentx_in ),
-// .rx8b10ben_in (rx8b10ben_in ),
-// .rxbufreset_in (rxbufreset_in ),
-// .rxcdrfreqreset_in (rxcdrfreqreset_in ),
-// .rxcdrhold_in (rxcdrhold_in ),
-// .rxcdrovrden_in (rxcdrovrden_in ),
-// .rxcdrreset_in (rxcdrreset_in ),
-// .rxcdrresetrsv_in (rxcdrresetrsv_in ),
-// .rxchbonden_in (rxchbonden_in ),
-// .rxchbondi_in (rxchbondi_in ),
-// .rxchbondlevel_in (rxchbondlevel_in ),
-// .rxchbondmaster_in (rxchbondmaster_in ),
-// .rxchbondslave_in (rxchbondslave_in ),
-// .rxcommadeten_in (rxcommadeten_in ),
-// .rxdfeagcctrl_in (rxdfeagcctrl_in ),
-// .rxdfeagchold_in (rxdfeagchold_in ),
-// .rxdfeagcovrden_in (rxdfeagcovrden_in ),
-// .rxdfelfhold_in (rxdfelfhold_in ),
-// .rxdfelfovrden_in (rxdfelfovrden_in ),
-// .rxdfelpmreset_in (rxdfelpmreset_in ),
-// .rxdfetap10hold_in (rxdfetap10hold_in ),
-// .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
-// .rxdfetap11hold_in (rxdfetap11hold_in ),
-// .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
-// .rxdfetap12hold_in (rxdfetap12hold_in ),
-// .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
-// .rxdfetap13hold_in (rxdfetap13hold_in ),
-// .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
-// .rxdfetap14hold_in (rxdfetap14hold_in ),
-// .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
-// .rxdfetap15hold_in (rxdfetap15hold_in ),
-// .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
-// .rxdfetap2hold_in (rxdfetap2hold_in ),
-// .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
-// .rxdfetap3hold_in (rxdfetap3hold_in ),
-// .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
-// .rxdfetap4hold_in (rxdfetap4hold_in ),
-// .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
-// .rxdfetap5hold_in (rxdfetap5hold_in ),
-// .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
-// .rxdfetap6hold_in (rxdfetap6hold_in ),
-// .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
-// .rxdfetap7hold_in (rxdfetap7hold_in ),
-// .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
-// .rxdfetap8hold_in (rxdfetap8hold_in ),
-// .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
-// .rxdfetap9hold_in (rxdfetap9hold_in ),
-// .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
-// .rxdfeuthold_in (rxdfeuthold_in ),
-// .rxdfeutovrden_in (rxdfeutovrden_in ),
-// .rxdfevphold_in (rxdfevphold_in ),
-// .rxdfevpovrden_in (rxdfevpovrden_in ),
-// .rxdfevsen_in (rxdfevsen_in ),
-// .rxdfexyden_in (rxdfexyden_in ),
-// .rxdlybypass_in (rxdlybypass_in ),
-// .rxdlyen_in (rxdlyen_in ),
-// .rxdlyovrden_in (rxdlyovrden_in ),
-// .rxdlysreset_in (rxdlysreset_in ),
-// .rxelecidlemode_in (rxelecidlemode_in ),
-// .rxgearboxslip_in (rxgearboxslip_in ),
-// .rxlatclk_in (rxlatclk_in ),
-// .rxlpmen_in (rxlpmen_in ),
-// .rxlpmgchold_in (rxlpmgchold_in ),
-// .rxlpmgcovrden_in (rxlpmgcovrden_in ),
-// .rxlpmhfhold_in (rxlpmhfhold_in ),
-// .rxlpmhfovrden_in (rxlpmhfovrden_in ),
-// .rxlpmlfhold_in (rxlpmlfhold_in ),
-// .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
-// .rxlpmoshold_in (rxlpmoshold_in ),
-// .rxlpmosovrden_in (rxlpmosovrden_in ),
-// .rxmcommaalignen_in (rxmcommaalignen_in ),
-// .rxmonitorsel_in (rxmonitorsel_in ),
-// .rxoobreset_in (rxoobreset_in ),
-// .rxoscalreset_in (rxoscalreset_in ),
-// .rxoshold_in (rxoshold_in ),
-// .rxosintcfg_in (rxosintcfg_in ),
-// .rxosinten_in (rxosinten_in ),
-// .rxosinthold_in (rxosinthold_in ),
-// .rxosintovrden_in (rxosintovrden_in ),
-// .rxosintstrobe_in (rxosintstrobe_in ),
-// .rxosinttestovrden_in (rxosinttestovrden_in ),
-// .rxosovrden_in (rxosovrden_in ),
-// .rxoutclksel_in (rxoutclksel_in ),
-// .rxpcommaalignen_in (rxpcommaalignen_in ),
-// .rxpcsreset_in (rxpcsreset_in ),
-// .rxpd_in (rxpd_in ),
-// .rxphalign_in (rxphalign_in ),
-// .rxphalignen_in (rxphalignen_in ),
-// .rxphdlypd_in (rxphdlypd_in ),
-// .rxphdlyreset_in (rxphdlyreset_in ),
-// .rxphovrden_in (rxphovrden_in ),
-// .rxpllclksel_in (rxpllclksel_in ),
-// .rxpmareset_in (rxpmareset_in ),
-// .rxpolarity_in (rxpolarity_in ),
-// .rxprbscntreset_in (rxprbscntreset_in ),
-// .rxprbssel_in (rxprbssel_in ),
-// .rxprogdivreset_in (rxprogdivreset_in ),
-// .rxqpien_in (rxqpien_in ),
-// .rxrate_in (rxrate_in ),
-// .rxratemode_in (rxratemode_in ),
-// .rxslide_in (rxslide_in ),
-// .rxslipoutclk_in (rxslipoutclk_in ),
-// .rxslippma_in (rxslippma_in ),
-// .rxsyncallin_in (rxsyncallin_in ),
-// .rxsyncin_in (rxsyncin_in ),
-// .rxsyncmode_in (rxsyncmode_in ),
-// .rxsysclksel_in (rxsysclksel_in ),
-// .rxuserrdy_in (rxuserrdy_in ),
-// .rxusrclk_in (rxusrclk_in ),
-// .rxusrclk2_in (rxusrclk2_in ),
-// .sigvalidclk_in (sigvalidclk_in ),
-// .tstin_in (tstin_in ),
-// .tx8b10bbypass_in (tx8b10bbypass_in ),
-// .tx8b10ben_in (tx8b10ben_in ),
-// .txbufdiffctrl_in (txbufdiffctrl_in ),
-// .txcominit_in (txcominit_in ),
-// .txcomsas_in (txcomsas_in ),
-// .txcomwake_in (txcomwake_in ),
-// .txctrl0_in (txctrl0_in ),
-// .txctrl1_in (txctrl1_in ),
-// .txctrl2_in (txctrl2_in ),
-// .txdata_in (txdata_in ),
-// .txdataextendrsvd_in (txdataextendrsvd_in ),
-// .txdeemph_in (txdeemph_in ),
-// .txdetectrx_in (txdetectrx_in ),
-// .txdiffctrl_in (txdiffctrl_in ),
-// .txdiffpd_in (txdiffpd_in ),
-// .txdlybypass_in (txdlybypass_in ),
-// .txdlyen_in (txdlyen_in ),
-// .txdlyhold_in (txdlyhold_in ),
-// .txdlyovrden_in (txdlyovrden_in ),
-// .txdlysreset_in (txdlysreset_in ),
-// .txdlyupdown_in (txdlyupdown_in ),
-// .txelecidle_in (txelecidle_in ),
-// .txheader_in (txheader_in ),
-// .txinhibit_in (txinhibit_in ),
-// .txlatclk_in (txlatclk_in ),
-// .txmaincursor_in (txmaincursor_in ),
-// .txmargin_in (txmargin_in ),
-// .txoutclksel_in (txoutclksel_in ),
-// .txpcsreset_in (txpcsreset_in ),
-// .txpd_in (txpd_in ),
-// .txpdelecidlemode_in (txpdelecidlemode_in ),
-// .txphalign_in (txphalign_in ),
-// .txphalignen_in (txphalignen_in ),
-// .txphdlypd_in (txphdlypd_in ),
-// .txphdlyreset_in (txphdlyreset_in ),
-// .txphdlytstclk_in (txphdlytstclk_in ),
-// .txphinit_in (txphinit_in ),
-// .txphovrden_in (txphovrden_in ),
-// .txpippmen_in (txpippmen_in ),
-// .txpippmovrden_in (txpippmovrden_in ),
-// .txpippmpd_in (txpippmpd_in ),
-// .txpippmsel_in (txpippmsel_in ),
-// .txpippmstepsize_in (txpippmstepsize_in ),
-// .txpisopd_in (txpisopd_in ),
-// .txpllclksel_in (txpllclksel_in ),
-// .txpmareset_in (txpmareset_in ),
-// .txpolarity_in (txpolarity_in ),
-// .txpostcursor_in (txpostcursor_in ),
-// .txpostcursorinv_in (txpostcursorinv_in ),
-// .txprbsforceerr_in (txprbsforceerr_in ),
-// .txprbssel_in (txprbssel_in ),
-// .txprecursor_in (txprecursor_in ),
-// .txprecursorinv_in (txprecursorinv_in ),
-// .txprogdivreset_in (txprogdivreset_in ),
-// .txqpibiasen_in (txqpibiasen_in ),
-// .txqpistrongpdown_in (txqpistrongpdown_in ),
-// .txqpiweakpup_in (txqpiweakpup_in ),
-// .txrate_in (txrate_in ),
-// .txratemode_in (txratemode_in ),
-// .txsequence_in (txsequence_in ),
-// .txswing_in (txswing_in ),
-// .txsyncallin_in (txsyncallin_in ),
-// .txsyncin_in (txsyncin_in ),
-// .txsyncmode_in (txsyncmode_in ),
-// .txsysclksel_in (txsysclksel_in ),
-// .txuserrdy_in (txuserrdy_in ),
-// .txusrclk_in (txusrclk_in ),
-// .txusrclk2_in (txusrclk2_in ),
-// .bufgtce_out (bufgtce_out ),
-// .bufgtcemask_out (bufgtcemask_out ),
-// .bufgtdiv_out (bufgtdiv_out ),
-// .bufgtreset_out (bufgtreset_out ),
-// .bufgtrstmask_out (bufgtrstmask_out ),
-// .cpllfbclklost_out (cpllfbclklost_out ),
-// .cplllock_out (cplllock_out ),
-// .cpllrefclklost_out (cpllrefclklost_out ),
-// .dmonitorout_out (dmonitorout_out ),
-// .drpdo_out (drpdo_out ),
-// .drprdy_out (drprdy_out ),
-// .eyescandataerror_out (eyescandataerror_out ),
-// .gthtxn_out (gthtxn_out ),
-// .gthtxp_out (gthtxp_out ),
-// .gtpowergood_out (gtpowergood_out ),
-// .gtrefclkmonitor_out (gtrefclkmonitor_out ),
-// .pcierategen3_out (pcierategen3_out ),
-// .pcierateidle_out (pcierateidle_out ),
-// .pcierateqpllpd_out (pcierateqpllpd_out ),
-// .pcierateqpllreset_out (pcierateqpllreset_out ),
-// .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
-// .pcieusergen3rdy_out (pcieusergen3rdy_out ),
-// .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
-// .pcieuserratestart_out (pcieuserratestart_out ),
-// .pcsrsvdout_out (pcsrsvdout_out ),
-// .phystatus_out (phystatus_out ),
-// .pinrsrvdas_out (pinrsrvdas_out ),
-// .resetexception_out (resetexception_out ),
-// .rxbufstatus_out (rxbufstatus_out ),
-// .rxbyteisaligned_out (rxbyteisaligned_out ),
-// .rxbyterealign_out (rxbyterealign_out ),
-// .rxcdrlock_out (rxcdrlock_out ),
-// .rxcdrphdone_out (rxcdrphdone_out ),
-// .rxchanbondseq_out (rxchanbondseq_out ),
-// .rxchanisaligned_out (rxchanisaligned_out ),
-// .rxchanrealign_out (rxchanrealign_out ),
-// .rxchbondo_out (rxchbondo_out ),
-// .rxclkcorcnt_out (rxclkcorcnt_out ),
-// .rxcominitdet_out (rxcominitdet_out ),
-// .rxcommadet_out (rxcommadet_out ),
-// .rxcomsasdet_out (rxcomsasdet_out ),
-// .rxcomwakedet_out (rxcomwakedet_out ),
-// .rxctrl0_out (rxctrl0_out ),
-// .rxctrl1_out (rxctrl1_out ),
-// .rxctrl2_out (rxctrl2_out ),
-// .rxctrl3_out (rxctrl3_out ),
-// .rxdata_out (rxdata_out ),
-// .rxdataextendrsvd_out (rxdataextendrsvd_out ),
-// .rxdatavalid_out (rxdatavalid_out ),
-// .rxdlysresetdone_out (rxdlysresetdone_out ),
-// .rxelecidle_out (rxelecidle_out ),
-// .rxheader_out (rxheader_out ),
-// .rxheadervalid_out (rxheadervalid_out ),
-// .rxmonitorout_out (rxmonitorout_out ),
-// .rxosintdone_out (rxosintdone_out ),
-// .rxosintstarted_out (rxosintstarted_out ),
-// .rxosintstrobedone_out (rxosintstrobedone_out ),
-// .rxosintstrobestarted_out (rxosintstrobestarted_out ),
-// .rxoutclk_out (rxoutclk_out ),
-// .rxoutclkfabric_out (rxoutclkfabric_out ),
-// .rxoutclkpcs_out (rxoutclkpcs_out ),
-// .rxphaligndone_out (rxphaligndone_out ),
-// .rxphalignerr_out (rxphalignerr_out ),
-// .rxpmaresetdone_out (rxpmaresetdone_out ),
-// .rxprbserr_out (rxprbserr_out ),
-// .rxprbslocked_out (rxprbslocked_out ),
-// .rxprgdivresetdone_out (rxprgdivresetdone_out ),
-// .rxqpisenn_out (rxqpisenn_out ),
-// .rxqpisenp_out (rxqpisenp_out ),
-// .rxratedone_out (rxratedone_out ),
-// .rxrecclkout_out (rxrecclkout_out ),
-// .rxresetdone_out (rxresetdone_out ),
-// .rxsliderdy_out (rxsliderdy_out ),
-// .rxslipdone_out (rxslipdone_out ),
-// .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
-// .rxslippmardy_out (rxslippmardy_out ),
-// .rxstartofseq_out (rxstartofseq_out ),
-// .rxstatus_out (rxstatus_out ),
-// .rxsyncdone_out (rxsyncdone_out ),
-// .rxsyncout_out (rxsyncout_out ),
-// .rxvalid_out (rxvalid_out ),
-// .txbufstatus_out (txbufstatus_out ),
-// .txcomfinish_out (txcomfinish_out ),
-// .txdlysresetdone_out (txdlysresetdone_out ),
-// .txoutclk_out (txoutclk_out ),
-// .txoutclkfabric_out (txoutclkfabric_out ),
-// .txoutclkpcs_out (txoutclkpcs_out ),
-// .txphaligndone_out (txphaligndone_out ),
-// .txphinitdone_out (txphinitdone_out ),
-// .txpmaresetdone_out (txpmaresetdone_out ),
-// .txprgdivresetdone_out (txprgdivresetdone_out ),
-// .txqpisenn_out (txqpisenn_out ),
-// .txqpisenp_out (txqpisenp_out ),
-// .txratedone_out (txratedone_out ),
-// .txresetdone_out (txresetdone_out ),
-// .txsyncdone_out (txsyncdone_out ),
-// .txsyncout_out (txsyncout_out )
-// );
-//
-// // Drive unused outputs to constant values
-// assign rxrecclk0sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign rxrecclk1sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign sdm0finalout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign sdm0testdata_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign sdm1finalout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign sdm1testdata_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign dmonitoroutclk_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign gtytxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign gtytxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign powerpresent_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxckcaldone_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpstresetdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpsu2lpexitdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpsu3wakedet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign txdccdone_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-
+ // Drive unused outputs to constant values
+ assign rxrecclk0sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign rxrecclk1sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign sdm0finalout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign sdm0testdata_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign sdm1finalout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign sdm1testdata_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign dmonitoroutclk_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gtytxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gtytxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign powerpresent_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxckcaldone_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpstresetdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpsu2lpexitdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpsu3wakedet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign txdccdone_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+*/
end
else if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTYE3) begin : gen_gtwizard_gtye3_top
+/*
+ // Generate GTYE3-type Transceivers Wizard submodule
+ gtwizard_ultrascale_2_gtwizard_gtye3 #(
+ .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
+ .C_PCIE_ENABLE (C_PCIE_ENABLE ),
+ .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
+ .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
+ .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
+ .C_GT_REV (C_GT_REV ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
+ .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
+ .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
+ .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
+ .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
+ .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
+ .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
+ .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
+ .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
+ .C_RX_ENABLE (C_RX_ENABLE ),
+ .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
+ .C_RX_LINE_RATE (C_RX_LINE_RATE ),
+ .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
+ .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
+ .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
+ .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
+ .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
+ .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
+ .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
+ .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
+ .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
+ .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
+ .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
+ .C_TX_ENABLE (C_TX_ENABLE ),
+ .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
+ .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
+ .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
+ .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
+ .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
+ .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
+ .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
+ ) gtwizard_ultrascale_2_gtwizard_gtye3_inst (
+ .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
+ .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
+ .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
+ .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
+ .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
+ .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
+ .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
+ .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
+ .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
+ .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
+ .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
+ .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
+ .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
+ .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
+ .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
+ .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
+ .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
+ .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
+ .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
+ .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
+ .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
+ .gtwiz_reset_all_in (gtwiz_reset_all_in ),
+ .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in),
+ .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
+ .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in),
+ .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
+ .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
+ .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
+ .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
+ .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
+ .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
+ .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
+ .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
+ .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
+ .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
+ .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
+ .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
+ .bgbypassb_in (bgbypassb_in ),
+ .bgmonitorenb_in (bgmonitorenb_in ),
+ .bgpdb_in (bgpdb_in ),
+ .bgrcalovrd_in (bgrcalovrd_in ),
+ .bgrcalovrdenb_in (bgrcalovrdenb_in ),
+ .drpaddr_common_in (drpaddr_common_in ),
+ .drpclk_common_in (drpclk_common_in ),
+ .drpdi_common_in (drpdi_common_in ),
+ .drpen_common_in (drpen_common_in ),
+ .drpwe_common_in (drpwe_common_in ),
+ .gtgrefclk0_in (gtgrefclk0_in ),
+ .gtgrefclk1_in (gtgrefclk1_in ),
+ .gtnorthrefclk00_in (gtnorthrefclk00_in ),
+ .gtnorthrefclk01_in (gtnorthrefclk01_in ),
+ .gtnorthrefclk10_in (gtnorthrefclk10_in ),
+ .gtnorthrefclk11_in (gtnorthrefclk11_in ),
+ .gtrefclk00_in (gtrefclk00_in ),
+ .gtrefclk01_in (gtrefclk01_in ),
+ .gtrefclk10_in (gtrefclk10_in ),
+ .gtrefclk11_in (gtrefclk11_in ),
+ .gtsouthrefclk00_in (gtsouthrefclk00_in ),
+ .gtsouthrefclk01_in (gtsouthrefclk01_in ),
+ .gtsouthrefclk10_in (gtsouthrefclk10_in ),
+ .gtsouthrefclk11_in (gtsouthrefclk11_in ),
+ .pmarsvd0_in (pmarsvd0_in ),
+ .pmarsvd1_in (pmarsvd1_in ),
+ .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
+ .qpll0lockdetclk_in (qpll0lockdetclk_in ),
+ .qpll0locken_in (qpll0locken_in ),
+ .qpll0pd_in (qpll0pd_in ),
+ .qpll0refclksel_in (qpll0refclksel_in ),
+ .qpll0reset_in (qpll0reset_in ),
+ .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
+ .qpll1lockdetclk_in (qpll1lockdetclk_in ),
+ .qpll1locken_in (qpll1locken_in ),
+ .qpll1pd_in (qpll1pd_in ),
+ .qpll1refclksel_in (qpll1refclksel_in ),
+ .qpll1reset_in (qpll1reset_in ),
+ .qpllrsvd1_in (qpllrsvd1_in ),
+ .qpllrsvd2_in (qpllrsvd2_in ),
+ .qpllrsvd3_in (qpllrsvd3_in ),
+ .qpllrsvd4_in (qpllrsvd4_in ),
+ .rcalenb_in (rcalenb_in ),
+ .sdm0data_in (sdm0data_in ),
+ .sdm0reset_in (sdm0reset_in ),
+ .sdm0width_in (sdm0width_in ),
+ .sdm1data_in (sdm1data_in ),
+ .sdm1reset_in (sdm1reset_in ),
+ .sdm1width_in (sdm1width_in ),
+ .drpdo_common_out (drpdo_common_out ),
+ .drprdy_common_out (drprdy_common_out ),
+ .pmarsvdout0_out (pmarsvdout0_out ),
+ .pmarsvdout1_out (pmarsvdout1_out ),
+ .qpll0fbclklost_out (qpll0fbclklost_out ),
+ .qpll0lock_out (qpll0lock_out ),
+ .qpll0outclk_out (qpll0outclk_out ),
+ .qpll0outrefclk_out (qpll0outrefclk_out ),
+ .qpll0refclklost_out (qpll0refclklost_out ),
+ .qpll1fbclklost_out (qpll1fbclklost_out ),
+ .qpll1lock_out (qpll1lock_out ),
+ .qpll1outclk_out (qpll1outclk_out ),
+ .qpll1outrefclk_out (qpll1outrefclk_out ),
+ .qpll1refclklost_out (qpll1refclklost_out ),
+ .qplldmonitor0_out (qplldmonitor0_out ),
+ .qplldmonitor1_out (qplldmonitor1_out ),
+ .refclkoutmonitor0_out (refclkoutmonitor0_out ),
+ .refclkoutmonitor1_out (refclkoutmonitor1_out ),
+ .rxrecclk0_sel_out (rxrecclk0_sel_out ),
+ .rxrecclk1_sel_out (rxrecclk1_sel_out ),
+ .sdm0finalout_out (sdm0finalout_out ),
+ .sdm0testdata_out (sdm0testdata_out ),
+ .sdm1finalout_out (sdm1finalout_out ),
+ .sdm1testdata_out (sdm1testdata_out ),
+ .cdrstepdir_in (cdrstepdir_in ),
+ .cdrstepsq_in (cdrstepsq_in ),
+ .cdrstepsx_in (cdrstepsx_in ),
+ .cfgreset_in (cfgreset_in ),
+ .clkrsvd0_in (clkrsvd0_in ),
+ .clkrsvd1_in (clkrsvd1_in ),
+ .cplllockdetclk_in (cplllockdetclk_in ),
+ .cplllocken_in (cplllocken_in ),
+ .cpllpd_in (cpllpd_in ),
+ .cpllrefclksel_in (cpllrefclksel_in ),
+ .cpllreset_in (cpllreset_in ),
+ .dmonfiforeset_in (dmonfiforeset_in ),
+ .dmonitorclk_in (dmonitorclk_in ),
+ .drpaddr_in (drpaddr_in ),
+ .drpclk_in (drpclk_in ),
+ .drpdi_in (drpdi_in ),
+ .drpen_in (drpen_in ),
+ .drpwe_in (drpwe_in ),
+ .elpcaldvorwren_in (elpcaldvorwren_in ),
+ .elpcalpaorwren_in (elpcalpaorwren_in ),
+ .evoddphicaldone_in (evoddphicaldone_in ),
+ .evoddphicalstart_in (evoddphicalstart_in ),
+ .evoddphidrden_in (evoddphidrden_in ),
+ .evoddphidwren_in (evoddphidwren_in ),
+ .evoddphixrden_in (evoddphixrden_in ),
+ .evoddphixwren_in (evoddphixwren_in ),
+ .eyescanmode_in (eyescanmode_in ),
+ .eyescanreset_in (eyescanreset_in ),
+ .eyescantrigger_in (eyescantrigger_in ),
+ .gtgrefclk_in (gtgrefclk_in ),
+ .gtnorthrefclk0_in (gtnorthrefclk0_in ),
+ .gtnorthrefclk1_in (gtnorthrefclk1_in ),
+ .gtrefclk0_in (gtrefclk0_in ),
+ .gtrefclk1_in (gtrefclk1_in ),
+ .gtresetsel_in (gtresetsel_in ),
+ .gtrsvd_in (gtrsvd_in ),
+ .gtrxreset_in (gtrxreset_in ),
+ .gtsouthrefclk0_in (gtsouthrefclk0_in ),
+ .gtsouthrefclk1_in (gtsouthrefclk1_in ),
+ .gttxreset_in (gttxreset_in ),
+ .gtyrxn_in (gtyrxn_in ),
+ .gtyrxp_in (gtyrxp_in ),
+ .loopback_in (loopback_in ),
+ .looprsvd_in (looprsvd_in ),
+ .lpbkrxtxseren_in (lpbkrxtxseren_in ),
+ .lpbktxrxseren_in (lpbktxrxseren_in ),
+ .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
+ .pcierstidle_in (pcierstidle_in ),
+ .pciersttxsyncstart_in (pciersttxsyncstart_in ),
+ .pcieuserratedone_in (pcieuserratedone_in ),
+ .pcsrsvdin_in (pcsrsvdin_in ),
+ .pcsrsvdin2_in (pcsrsvdin2_in ),
+ .pmarsvdin_in (pmarsvdin_in ),
+ .qpll0clk_in (qpll0clk_in ),
+ .qpll0refclk_in (qpll0refclk_in ),
+ .qpll1clk_in (qpll1clk_in ),
+ .qpll1refclk_in (qpll1refclk_in ),
+ .resetovrd_in (resetovrd_in ),
+ .rstclkentx_in (rstclkentx_in ),
+ .rx8b10ben_in (rx8b10ben_in ),
+ .rxbufreset_in (rxbufreset_in ),
+ .rxcdrfreqreset_in (rxcdrfreqreset_in ),
+ .rxcdrhold_in (rxcdrhold_in ),
+ .rxcdrovrden_in (rxcdrovrden_in ),
+ .rxcdrreset_in (rxcdrreset_in ),
+ .rxcdrresetrsv_in (rxcdrresetrsv_in ),
+ .rxchbonden_in (rxchbonden_in ),
+ .rxchbondi_in (rxchbondi_in ),
+ .rxchbondlevel_in (rxchbondlevel_in ),
+ .rxchbondmaster_in (rxchbondmaster_in ),
+ .rxchbondslave_in (rxchbondslave_in ),
+ .rxckcalreset_in (rxckcalreset_in ),
+ .rxcommadeten_in (rxcommadeten_in ),
+ .rxdccforcestart_in (rxdccforcestart_in ),
+ .rxdfeagchold_in (rxdfeagchold_in ),
+ .rxdfeagcovrden_in (rxdfeagcovrden_in ),
+ .rxdfelfhold_in (rxdfelfhold_in ),
+ .rxdfelfovrden_in (rxdfelfovrden_in ),
+ .rxdfelpmreset_in (rxdfelpmreset_in ),
+ .rxdfetap10hold_in (rxdfetap10hold_in ),
+ .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
+ .rxdfetap11hold_in (rxdfetap11hold_in ),
+ .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
+ .rxdfetap12hold_in (rxdfetap12hold_in ),
+ .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
+ .rxdfetap13hold_in (rxdfetap13hold_in ),
+ .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
+ .rxdfetap14hold_in (rxdfetap14hold_in ),
+ .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
+ .rxdfetap15hold_in (rxdfetap15hold_in ),
+ .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
+ .rxdfetap2hold_in (rxdfetap2hold_in ),
+ .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
+ .rxdfetap3hold_in (rxdfetap3hold_in ),
+ .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
+ .rxdfetap4hold_in (rxdfetap4hold_in ),
+ .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
+ .rxdfetap5hold_in (rxdfetap5hold_in ),
+ .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
+ .rxdfetap6hold_in (rxdfetap6hold_in ),
+ .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
+ .rxdfetap7hold_in (rxdfetap7hold_in ),
+ .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
+ .rxdfetap8hold_in (rxdfetap8hold_in ),
+ .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
+ .rxdfetap9hold_in (rxdfetap9hold_in ),
+ .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
+ .rxdfeuthold_in (rxdfeuthold_in ),
+ .rxdfeutovrden_in (rxdfeutovrden_in ),
+ .rxdfevphold_in (rxdfevphold_in ),
+ .rxdfevpovrden_in (rxdfevpovrden_in ),
+ .rxdfevsen_in (rxdfevsen_in ),
+ .rxdfexyden_in (rxdfexyden_in ),
+ .rxdlybypass_in (rxdlybypass_in ),
+ .rxdlyen_in (rxdlyen_in ),
+ .rxdlyovrden_in (rxdlyovrden_in ),
+ .rxdlysreset_in (rxdlysreset_in ),
+ .rxelecidlemode_in (rxelecidlemode_in ),
+ .rxgearboxslip_in (rxgearboxslip_in ),
+ .rxlatclk_in (rxlatclk_in ),
+ .rxlpmen_in (rxlpmen_in ),
+ .rxlpmgchold_in (rxlpmgchold_in ),
+ .rxlpmgcovrden_in (rxlpmgcovrden_in ),
+ .rxlpmhfhold_in (rxlpmhfhold_in ),
+ .rxlpmhfovrden_in (rxlpmhfovrden_in ),
+ .rxlpmlfhold_in (rxlpmlfhold_in ),
+ .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
+ .rxlpmoshold_in (rxlpmoshold_in ),
+ .rxlpmosovrden_in (rxlpmosovrden_in ),
+ .rxmcommaalignen_in (rxmcommaalignen_in ),
+ .rxmonitorsel_in (rxmonitorsel_in ),
+ .rxoobreset_in (rxoobreset_in ),
+ .rxoscalreset_in (rxoscalreset_in ),
+ .rxoshold_in (rxoshold_in ),
+ .rxosintcfg_in (rxosintcfg_in ),
+ .rxosinten_in (rxosinten_in ),
+ .rxosinthold_in (rxosinthold_in ),
+ .rxosintovrden_in (rxosintovrden_in ),
+ .rxosintstrobe_in (rxosintstrobe_in ),
+ .rxosinttestovrden_in (rxosinttestovrden_in ),
+ .rxosovrden_in (rxosovrden_in ),
+ .rxoutclksel_in (rxoutclksel_in ),
+ .rxpcommaalignen_in (rxpcommaalignen_in ),
+ .rxpcsreset_in (rxpcsreset_in ),
+ .rxpd_in (rxpd_in ),
+ .rxphalign_in (rxphalign_in ),
+ .rxphalignen_in (rxphalignen_in ),
+ .rxphdlypd_in (rxphdlypd_in ),
+ .rxphdlyreset_in (rxphdlyreset_in ),
+ .rxphovrden_in (rxphovrden_in ),
+ .rxpllclksel_in (rxpllclksel_in ),
+ .rxpmareset_in (rxpmareset_in ),
+ .rxpolarity_in (rxpolarity_in ),
+ .rxprbscntreset_in (rxprbscntreset_in ),
+ .rxprbssel_in (rxprbssel_in ),
+ .rxprogdivreset_in (rxprogdivreset_in ),
+ .rxrate_in (rxrate_in ),
+ .rxratemode_in (rxratemode_in ),
+ .rxslide_in (rxslide_in ),
+ .rxslipoutclk_in (rxslipoutclk_in ),
+ .rxslippma_in (rxslippma_in ),
+ .rxsyncallin_in (rxsyncallin_in ),
+ .rxsyncin_in (rxsyncin_in ),
+ .rxsyncmode_in (rxsyncmode_in ),
+ .rxsysclksel_in (rxsysclksel_in ),
+ .rxuserrdy_in (rxuserrdy_in ),
+ .rxusrclk_in (rxusrclk_in ),
+ .rxusrclk2_in (rxusrclk2_in ),
+ .sigvalidclk_in (sigvalidclk_in ),
+ .tstin_in (tstin_in ),
+ .tx8b10bbypass_in (tx8b10bbypass_in ),
+ .tx8b10ben_in (tx8b10ben_in ),
+ .txbufdiffctrl_in (txbufdiffctrl_in ),
+ .txcominit_in (txcominit_in ),
+ .txcomsas_in (txcomsas_in ),
+ .txcomwake_in (txcomwake_in ),
+ .txctrl0_in (txctrl0_in ),
+ .txctrl1_in (txctrl1_in ),
+ .txctrl2_in (txctrl2_in ),
+ .txdata_in (txdata_in ),
+ .txdataextendrsvd_in (txdataextendrsvd_in ),
+ .txdccforcestart_in (txdccforcestart_in ),
+ .txdccreset_in (txdccreset_in ),
+ .txdeemph_in (txdeemph_in ),
+ .txdetectrx_in (txdetectrx_in ),
+ .txdiffctrl_in (txdiffctrl_in ),
+ .txdiffpd_in (txdiffpd_in ),
+ .txdlybypass_in (txdlybypass_in ),
+ .txdlyen_in (txdlyen_in ),
+ .txdlyhold_in (txdlyhold_in ),
+ .txdlyovrden_in (txdlyovrden_in ),
+ .txdlysreset_in (txdlysreset_in ),
+ .txdlyupdown_in (txdlyupdown_in ),
+ .txelecidle_in (txelecidle_in ),
+ .txelforcestart_in (txelforcestart_in ),
+ .txheader_in (txheader_in ),
+ .txinhibit_in (txinhibit_in ),
+ .txlatclk_in (txlatclk_in ),
+ .txmaincursor_in (txmaincursor_in ),
+ .txmargin_in (txmargin_in ),
+ .txoutclksel_in (txoutclksel_in ),
+ .txpcsreset_in (txpcsreset_in ),
+ .txpd_in (txpd_in ),
+ .txpdelecidlemode_in (txpdelecidlemode_in ),
+ .txphalign_in (txphalign_in ),
+ .txphalignen_in (txphalignen_in ),
+ .txphdlypd_in (txphdlypd_in ),
+ .txphdlyreset_in (txphdlyreset_in ),
+ .txphdlytstclk_in (txphdlytstclk_in ),
+ .txphinit_in (txphinit_in ),
+ .txphovrden_in (txphovrden_in ),
+ .txpippmen_in (txpippmen_in ),
+ .txpippmovrden_in (txpippmovrden_in ),
+ .txpippmpd_in (txpippmpd_in ),
+ .txpippmsel_in (txpippmsel_in ),
+ .txpippmstepsize_in (txpippmstepsize_in ),
+ .txpisopd_in (txpisopd_in ),
+ .txpllclksel_in (txpllclksel_in ),
+ .txpmareset_in (txpmareset_in ),
+ .txpolarity_in (txpolarity_in ),
+ .txpostcursor_in (txpostcursor_in ),
+ .txprbsforceerr_in (txprbsforceerr_in ),
+ .txprbssel_in (txprbssel_in ),
+ .txprecursor_in (txprecursor_in ),
+ .txprogdivreset_in (txprogdivreset_in ),
+ .txrate_in (txrate_in ),
+ .txratemode_in (txratemode_in ),
+ .txsequence_in (txsequence_in ),
+ .txswing_in (txswing_in ),
+ .txsyncallin_in (txsyncallin_in ),
+ .txsyncin_in (txsyncin_in ),
+ .txsyncmode_in (txsyncmode_in ),
+ .txsysclksel_in (txsysclksel_in ),
+ .txuserrdy_in (txuserrdy_in ),
+ .txusrclk_in (txusrclk_in ),
+ .txusrclk2_in (txusrclk2_in ),
+ .bufgtce_out (bufgtce_out ),
+ .bufgtcemask_out (bufgtcemask_out ),
+ .bufgtdiv_out (bufgtdiv_out ),
+ .bufgtreset_out (bufgtreset_out ),
+ .bufgtrstmask_out (bufgtrstmask_out ),
+ .cpllfbclklost_out (cpllfbclklost_out ),
+ .cplllock_out (cplllock_out ),
+ .cpllrefclklost_out (cpllrefclklost_out ),
+ .dmonitorout_out (dmonitorout_out ),
+ .drpdo_out (drpdo_out ),
+ .drprdy_out (drprdy_out ),
+ .eyescandataerror_out (eyescandataerror_out ),
+ .gtpowergood_out (gtpowergood_out ),
+ .gtrefclkmonitor_out (gtrefclkmonitor_out ),
+ .gtytxn_out (gtytxn_out ),
+ .gtytxp_out (gtytxp_out ),
+ .pcierategen3_out (pcierategen3_out ),
+ .pcierateidle_out (pcierateidle_out ),
+ .pcierateqpllpd_out (pcierateqpllpd_out ),
+ .pcierateqpllreset_out (pcierateqpllreset_out ),
+ .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
+ .pcieusergen3rdy_out (pcieusergen3rdy_out ),
+ .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
+ .pcieuserratestart_out (pcieuserratestart_out ),
+ .pcsrsvdout_out (pcsrsvdout_out ),
+ .phystatus_out (phystatus_out ),
+ .pinrsrvdas_out (pinrsrvdas_out ),
+ .resetexception_out (resetexception_out ),
+ .rxbufstatus_out (rxbufstatus_out ),
+ .rxbyteisaligned_out (rxbyteisaligned_out ),
+ .rxbyterealign_out (rxbyterealign_out ),
+ .rxcdrlock_out (rxcdrlock_out ),
+ .rxcdrphdone_out (rxcdrphdone_out ),
+ .rxchanbondseq_out (rxchanbondseq_out ),
+ .rxchanisaligned_out (rxchanisaligned_out ),
+ .rxchanrealign_out (rxchanrealign_out ),
+ .rxchbondo_out (rxchbondo_out ),
+ .rxckcaldone_out (rxckcaldone_out ),
+ .rxclkcorcnt_out (rxclkcorcnt_out ),
+ .rxcominitdet_out (rxcominitdet_out ),
+ .rxcommadet_out (rxcommadet_out ),
+ .rxcomsasdet_out (rxcomsasdet_out ),
+ .rxcomwakedet_out (rxcomwakedet_out ),
+ .rxctrl0_out (rxctrl0_out ),
+ .rxctrl1_out (rxctrl1_out ),
+ .rxctrl2_out (rxctrl2_out ),
+ .rxctrl3_out (rxctrl3_out ),
+ .rxdata_out (rxdata_out ),
+ .rxdataextendrsvd_out (rxdataextendrsvd_out ),
+ .rxdatavalid_out (rxdatavalid_out ),
+ .rxdlysresetdone_out (rxdlysresetdone_out ),
+ .rxelecidle_out (rxelecidle_out ),
+ .rxheader_out (rxheader_out ),
+ .rxheadervalid_out (rxheadervalid_out ),
+ .rxmonitorout_out (rxmonitorout_out ),
+ .rxosintdone_out (rxosintdone_out ),
+ .rxosintstarted_out (rxosintstarted_out ),
+ .rxosintstrobedone_out (rxosintstrobedone_out ),
+ .rxosintstrobestarted_out (rxosintstrobestarted_out ),
+ .rxoutclk_out (rxoutclk_out ),
+ .rxoutclkfabric_out (rxoutclkfabric_out ),
+ .rxoutclkpcs_out (rxoutclkpcs_out ),
+ .rxphaligndone_out (rxphaligndone_out ),
+ .rxphalignerr_out (rxphalignerr_out ),
+ .rxpmaresetdone_out (rxpmaresetdone_out ),
+ .rxprbserr_out (rxprbserr_out ),
+ .rxprbslocked_out (rxprbslocked_out ),
+ .rxprgdivresetdone_out (rxprgdivresetdone_out ),
+ .rxratedone_out (rxratedone_out ),
+ .rxrecclkout_out (rxrecclkout_out ),
+ .rxresetdone_out (rxresetdone_out ),
+ .rxsliderdy_out (rxsliderdy_out ),
+ .rxslipdone_out (rxslipdone_out ),
+ .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
+ .rxslippmardy_out (rxslippmardy_out ),
+ .rxstartofseq_out (rxstartofseq_out ),
+ .rxstatus_out (rxstatus_out ),
+ .rxsyncdone_out (rxsyncdone_out ),
+ .rxsyncout_out (rxsyncout_out ),
+ .rxvalid_out (rxvalid_out ),
+ .txbufstatus_out (txbufstatus_out ),
+ .txcomfinish_out (txcomfinish_out ),
+ .txdccdone_out (txdccdone_out ),
+ .txdlysresetdone_out (txdlysresetdone_out ),
+ .txoutclk_out (txoutclk_out ),
+ .txoutclkfabric_out (txoutclkfabric_out ),
+ .txoutclkpcs_out (txoutclkpcs_out ),
+ .txphaligndone_out (txphaligndone_out ),
+ .txphinitdone_out (txphinitdone_out ),
+ .txpmaresetdone_out (txpmaresetdone_out ),
+ .txprgdivresetdone_out (txprgdivresetdone_out ),
+ .txratedone_out (txratedone_out ),
+ .txresetdone_out (txresetdone_out ),
+ .txsyncdone_out (txsyncdone_out ),
+ .txsyncout_out (txsyncout_out )
+ );
+
+ // Drive unused outputs to constant values
+ assign rxrecclk0sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign rxrecclk1sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign dmonitoroutclk_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gthtxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gthtxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign powerpresent_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpstresetdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpsu2lpexitdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxlfpsu3wakedet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign txqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign txqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+*/
+ end
+ else if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTHE4) begin : gen_gtwizard_gthe4_top
+
+ // Generate GTHE4-type Transceivers Wizard submodule
+ gtwizard_ultrascale_2_gtwizard_gthe4 #(
+ .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
+ .C_PCIE_ENABLE (C_PCIE_ENABLE ),
+ .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
+ .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
+ .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
+ .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
+ .C_GT_REV (C_GT_REV ),
+ .C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
+ .C_USER_GTPOWERGOOD_DELAY_EN (C_USER_GTPOWERGOOD_DELAY_EN ),
+ .C_SIM_CPLL_CAL_BYPASS (C_SIM_CPLL_CAL_BYPASS ),
+ .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
+ .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
+ .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
+ .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
+ .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
+ .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
+ .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
+ .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
+ .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
+ .C_RX_ENABLE (C_RX_ENABLE ),
+ .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
+ .C_RX_LINE_RATE (C_RX_LINE_RATE ),
+ .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
+ .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
+ .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
+ .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
+ .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
+ .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
+ .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
+ .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
+ .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
+ .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
+ .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
+ .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
+ .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
+ .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
+ .C_TX_ENABLE (C_TX_ENABLE ),
+ .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
+ .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
+ .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
+ .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
+ .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
+ .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
+ .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
+ .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
+ .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
+ ) gtwizard_ultrascale_2_gtwizard_gthe4_inst (
+ .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
+ .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
+ .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
+ .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
+ .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
+ .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
+ .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
+ .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
+ .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
+ .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
+ .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
+ .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
+ .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
+ .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
+ .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
+ .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
+ .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
+ .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
+ .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
+ .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
+ .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
+ .gtwiz_reset_all_in (gtwiz_reset_all_in ),
+ .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in),
+ .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
+ .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in),
+ .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
+ .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
+ .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
+ .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
+ .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
+ .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
+ .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
+ .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
+ .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
+ .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
+ .gtwiz_gthe4_cpll_cal_txoutclk_period_in (gtwiz_gthe4_cpll_cal_txoutclk_period_in),
+ .gtwiz_gthe4_cpll_cal_cnt_tol_in (gtwiz_gthe4_cpll_cal_cnt_tol_in ),
+ .gtwiz_gthe4_cpll_cal_bufg_ce_in (gtwiz_gthe4_cpll_cal_bufg_ce_in ),
+ .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
+ .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
+ .bgbypassb_in (bgbypassb_in ),
+ .bgmonitorenb_in (bgmonitorenb_in ),
+ .bgpdb_in (bgpdb_in ),
+ .bgrcalovrd_in (bgrcalovrd_in ),
+ .bgrcalovrdenb_in (bgrcalovrdenb_in ),
+ .drpaddr_common_in (drpaddr_common_in ),
+ .drpclk_common_in (drpclk_common_in ),
+ .drpdi_common_in (drpdi_common_in ),
+ .drpen_common_in (drpen_common_in ),
+ .drpwe_common_in (drpwe_common_in ),
+ .gtgrefclk0_in (gtgrefclk0_in ),
+ .gtgrefclk1_in (gtgrefclk1_in ),
+ .gtnorthrefclk00_in (gtnorthrefclk00_in ),
+ .gtnorthrefclk01_in (gtnorthrefclk01_in ),
+ .gtnorthrefclk10_in (gtnorthrefclk10_in ),
+ .gtnorthrefclk11_in (gtnorthrefclk11_in ),
+ .gtrefclk00_in (gtrefclk00_in ),
+ .gtrefclk01_in (gtrefclk01_in ),
+ .gtrefclk10_in (gtrefclk10_in ),
+ .gtrefclk11_in (gtrefclk11_in ),
+ .gtsouthrefclk00_in (gtsouthrefclk00_in ),
+ .gtsouthrefclk01_in (gtsouthrefclk01_in ),
+ .gtsouthrefclk10_in (gtsouthrefclk10_in ),
+ .gtsouthrefclk11_in (gtsouthrefclk11_in ),
+ .pcierateqpll0_in (pcierateqpll0_in ),
+ .pcierateqpll1_in (pcierateqpll1_in ),
+ .pmarsvd0_in (pmarsvd0_in ),
+ .pmarsvd1_in (pmarsvd1_in ),
+ .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
+ .qpll0clkrsvd1_in (qpll0clkrsvd1_in ),
+ .qpll0fbdiv_in (qpll0fbdiv_in ),
+ .qpll0lockdetclk_in (qpll0lockdetclk_in ),
+ .qpll0locken_in (qpll0locken_in ),
+ .qpll0pd_in (qpll0pd_in ),
+ .qpll0refclksel_in (qpll0refclksel_in ),
+ .qpll0reset_in (qpll0reset_in ),
+ .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
+ .qpll1clkrsvd1_in (qpll1clkrsvd1_in ),
+ .qpll1fbdiv_in (qpll1fbdiv_in ),
+ .qpll1lockdetclk_in (qpll1lockdetclk_in ),
+ .qpll1locken_in (qpll1locken_in ),
+ .qpll1pd_in (qpll1pd_in ),
+ .qpll1refclksel_in (qpll1refclksel_in ),
+ .qpll1reset_in (qpll1reset_in ),
+ .qpllrsvd1_in (qpllrsvd1_in ),
+ .qpllrsvd2_in (qpllrsvd2_in ),
+ .qpllrsvd3_in (qpllrsvd3_in ),
+ .qpllrsvd4_in (qpllrsvd4_in ),
+ .rcalenb_in (rcalenb_in ),
+ .sdm0data_in (sdm0data_in ),
+ .sdm0reset_in (sdm0reset_in ),
+ .sdm0toggle_in (sdm0toggle_in ),
+ .sdm0width_in (sdm0width_in ),
+ .sdm1data_in (sdm1data_in ),
+ .sdm1reset_in (sdm1reset_in ),
+ .sdm1toggle_in (sdm1toggle_in ),
+ .sdm1width_in (sdm1width_in ),
+ .tcongpi_in (tcongpi_in ),
+ .tconpowerup_in (tconpowerup_in ),
+ .tconreset_in (tconreset_in ),
+ .tconrsvdin1_in (tconrsvdin1_in ),
+ .drpdo_common_out (drpdo_common_out ),
+ .drprdy_common_out (drprdy_common_out ),
+ .pmarsvdout0_out (pmarsvdout0_out ),
+ .pmarsvdout1_out (pmarsvdout1_out ),
+ .qpll0fbclklost_out (qpll0fbclklost_out ),
+ .qpll0lock_out (qpll0lock_out ),
+ .qpll0outclk_out (qpll0outclk_out ),
+ .qpll0outrefclk_out (qpll0outrefclk_out ),
+ .qpll0refclklost_out (qpll0refclklost_out ),
+ .qpll1fbclklost_out (qpll1fbclklost_out ),
+ .qpll1lock_out (qpll1lock_out ),
+ .qpll1outclk_out (qpll1outclk_out ),
+ .qpll1outrefclk_out (qpll1outrefclk_out ),
+ .qpll1refclklost_out (qpll1refclklost_out ),
+ .qplldmonitor0_out (qplldmonitor0_out ),
+ .qplldmonitor1_out (qplldmonitor1_out ),
+ .refclkoutmonitor0_out (refclkoutmonitor0_out ),
+ .refclkoutmonitor1_out (refclkoutmonitor1_out ),
+ .rxrecclk0sel_out (rxrecclk0sel_out ),
+ .rxrecclk1sel_out (rxrecclk1sel_out ),
+ .sdm0finalout_out (sdm0finalout_out ),
+ .sdm0testdata_out (sdm0testdata_out ),
+ .sdm1finalout_out (sdm1finalout_out ),
+ .sdm1testdata_out (sdm1testdata_out ),
+ .tcongpo_out (tcongpo_out ),
+ .tconrsvdout0_out (tconrsvdout0_out ),
+ .cdrstepdir_in (cdrstepdir_in ),
+ .cdrstepsq_in (cdrstepsq_in ),
+ .cdrstepsx_in (cdrstepsx_in ),
+ .cfgreset_in (cfgreset_in ),
+ .clkrsvd0_in (clkrsvd0_in ),
+ .clkrsvd1_in (clkrsvd1_in ),
+ .cpllfreqlock_in (cpllfreqlock_in ),
+ .cplllockdetclk_in (cplllockdetclk_in ),
+ .cplllocken_in (cplllocken_in ),
+ .cpllpd_in (cpllpd_in ),
+ .cpllrefclksel_in (cpllrefclksel_in ),
+ .cpllreset_in (cpllreset_in ),
+ .dmonfiforeset_in (dmonfiforeset_in ),
+ .dmonitorclk_in (dmonitorclk_in ),
+ .drpaddr_in (drpaddr_in ),
+ .drpclk_in (drpclk_in ),
+ .drpdi_in (drpdi_in ),
+ .drpen_in (drpen_in ),
+ .drprst_in (drprst_in ),
+ .drpwe_in (drpwe_in ),
+ .eyescanreset_in (eyescanreset_in ),
+ .eyescantrigger_in (eyescantrigger_in ),
+ .freqos_in (freqos_in ),
+ .gtgrefclk_in (gtgrefclk_in ),
+ .gthrxn_in (gthrxn_in ),
+ .gthrxp_in (gthrxp_in ),
+ .gtnorthrefclk0_in (gtnorthrefclk0_in ),
+ .gtnorthrefclk1_in (gtnorthrefclk1_in ),
+ .gtrefclk0_in (gtrefclk0_in ),
+ .gtrefclk1_in (gtrefclk1_in ),
+ .gtrsvd_in (gtrsvd_in ),
+ .gtrxreset_in (gtrxreset_in ),
+ .gtrxresetsel_in (gtrxresetsel_in ),
+ .gtsouthrefclk0_in (gtsouthrefclk0_in ),
+ .gtsouthrefclk1_in (gtsouthrefclk1_in ),
+ .gttxreset_in (gttxreset_in ),
+ .gttxresetsel_in (gttxresetsel_in ),
+ .incpctrl_in (incpctrl_in ),
+ .loopback_in (loopback_in ),
+ .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
+ .pcierstidle_in (pcierstidle_in ),
+ .pciersttxsyncstart_in (pciersttxsyncstart_in ),
+ .pcieuserratedone_in (pcieuserratedone_in ),
+ .pcsrsvdin_in (pcsrsvdin_in ),
+ .qpll0clk_in (qpll0clk_in ),
+ .qpll0freqlock_in (qpll0freqlock_in ),
+ .qpll0refclk_in (qpll0refclk_in ),
+ .qpll1clk_in (qpll1clk_in ),
+ .qpll1freqlock_in (qpll1freqlock_in ),
+ .qpll1refclk_in (qpll1refclk_in ),
+ .resetovrd_in (resetovrd_in ),
+ .rx8b10ben_in (rx8b10ben_in ),
+ .rxafecfoken_in (rxafecfoken_in ),
+ .rxbufreset_in (rxbufreset_in ),
+ .rxcdrfreqreset_in (rxcdrfreqreset_in ),
+ .rxcdrhold_in (rxcdrhold_in ),
+ .rxcdrovrden_in (rxcdrovrden_in ),
+ .rxcdrreset_in (rxcdrreset_in ),
+ .rxchbonden_in (rxchbonden_in ),
+ .rxchbondi_in (rxchbondi_in ),
+ .rxchbondlevel_in (rxchbondlevel_in ),
+ .rxchbondmaster_in (rxchbondmaster_in ),
+ .rxchbondslave_in (rxchbondslave_in ),
+ .rxckcalreset_in (rxckcalreset_in ),
+ .rxckcalstart_in (rxckcalstart_in ),
+ .rxcommadeten_in (rxcommadeten_in ),
+ .rxdfeagcctrl_in (rxdfeagcctrl_in ),
+ .rxdfeagchold_in (rxdfeagchold_in ),
+ .rxdfeagcovrden_in (rxdfeagcovrden_in ),
+ .rxdfecfokfcnum_in (rxdfecfokfcnum_in ),
+ .rxdfecfokfen_in (rxdfecfokfen_in ),
+ .rxdfecfokfpulse_in (rxdfecfokfpulse_in ),
+ .rxdfecfokhold_in (rxdfecfokhold_in ),
+ .rxdfecfokovren_in (rxdfecfokovren_in ),
+ .rxdfekhhold_in (rxdfekhhold_in ),
+ .rxdfekhovrden_in (rxdfekhovrden_in ),
+ .rxdfelfhold_in (rxdfelfhold_in ),
+ .rxdfelfovrden_in (rxdfelfovrden_in ),
+ .rxdfelpmreset_in (rxdfelpmreset_in ),
+ .rxdfetap10hold_in (rxdfetap10hold_in ),
+ .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
+ .rxdfetap11hold_in (rxdfetap11hold_in ),
+ .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
+ .rxdfetap12hold_in (rxdfetap12hold_in ),
+ .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
+ .rxdfetap13hold_in (rxdfetap13hold_in ),
+ .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
+ .rxdfetap14hold_in (rxdfetap14hold_in ),
+ .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
+ .rxdfetap15hold_in (rxdfetap15hold_in ),
+ .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
+ .rxdfetap2hold_in (rxdfetap2hold_in ),
+ .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
+ .rxdfetap3hold_in (rxdfetap3hold_in ),
+ .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
+ .rxdfetap4hold_in (rxdfetap4hold_in ),
+ .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
+ .rxdfetap5hold_in (rxdfetap5hold_in ),
+ .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
+ .rxdfetap6hold_in (rxdfetap6hold_in ),
+ .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
+ .rxdfetap7hold_in (rxdfetap7hold_in ),
+ .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
+ .rxdfetap8hold_in (rxdfetap8hold_in ),
+ .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
+ .rxdfetap9hold_in (rxdfetap9hold_in ),
+ .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
+ .rxdfeuthold_in (rxdfeuthold_in ),
+ .rxdfeutovrden_in (rxdfeutovrden_in ),
+ .rxdfevphold_in (rxdfevphold_in ),
+ .rxdfevpovrden_in (rxdfevpovrden_in ),
+ .rxdfexyden_in (rxdfexyden_in ),
+ .rxdlybypass_in (rxdlybypass_in ),
+ .rxdlyen_in (rxdlyen_in ),
+ .rxdlyovrden_in (rxdlyovrden_in ),
+ .rxdlysreset_in (rxdlysreset_in ),
+ .rxelecidlemode_in (rxelecidlemode_in ),
+ .rxeqtraining_in (rxeqtraining_in ),
+ .rxgearboxslip_in (rxgearboxslip_in ),
+ .rxlatclk_in (rxlatclk_in ),
+ .rxlpmen_in (rxlpmen_in ),
+ .rxlpmgchold_in (rxlpmgchold_in ),
+ .rxlpmgcovrden_in (rxlpmgcovrden_in ),
+ .rxlpmhfhold_in (rxlpmhfhold_in ),
+ .rxlpmhfovrden_in (rxlpmhfovrden_in ),
+ .rxlpmlfhold_in (rxlpmlfhold_in ),
+ .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
+ .rxlpmoshold_in (rxlpmoshold_in ),
+ .rxlpmosovrden_in (rxlpmosovrden_in ),
+ .rxmcommaalignen_in (rxmcommaalignen_in ),
+ .rxmonitorsel_in (rxmonitorsel_in ),
+ .rxoobreset_in (rxoobreset_in ),
+ .rxoscalreset_in (rxoscalreset_in ),
+ .rxoshold_in (rxoshold_in ),
+ .rxosovrden_in (rxosovrden_in ),
+ .rxoutclksel_in (rxoutclksel_in ),
+ .rxpcommaalignen_in (rxpcommaalignen_in ),
+ .rxpcsreset_in (rxpcsreset_in ),
+ .rxpd_in (rxpd_in ),
+ .rxphalign_in (rxphalign_in ),
+ .rxphalignen_in (rxphalignen_in ),
+ .rxphdlypd_in (rxphdlypd_in ),
+ .rxphdlyreset_in (rxphdlyreset_in ),
+ .rxphovrden_in (rxphovrden_in ),
+ .rxpllclksel_in (rxpllclksel_in ),
+ .rxpmareset_in (rxpmareset_in ),
+ .rxpolarity_in (rxpolarity_in ),
+ .rxprbscntreset_in (rxprbscntreset_in ),
+ .rxprbssel_in (rxprbssel_in ),
+ .rxprogdivreset_in (rxprogdivreset_in ),
+ .rxqpien_in (rxqpien_in ),
+ .rxrate_in (rxrate_in ),
+ .rxratemode_in (rxratemode_in ),
+ .rxslide_in (rxslide_in ),
+ .rxslipoutclk_in (rxslipoutclk_in ),
+ .rxslippma_in (rxslippma_in ),
+ .rxsyncallin_in (rxsyncallin_in ),
+ .rxsyncin_in (rxsyncin_in ),
+ .rxsyncmode_in (rxsyncmode_in ),
+ .rxsysclksel_in (rxsysclksel_in ),
+ .rxtermination_in (rxtermination_in ),
+ .rxuserrdy_in (rxuserrdy_in ),
+ .rxusrclk_in (rxusrclk_in ),
+ .rxusrclk2_in (rxusrclk2_in ),
+ .sigvalidclk_in (sigvalidclk_in ),
+ .tstin_in (tstin_in ),
+ .tx8b10bbypass_in (tx8b10bbypass_in ),
+ .tx8b10ben_in (tx8b10ben_in ),
+ .txcominit_in (txcominit_in ),
+ .txcomsas_in (txcomsas_in ),
+ .txcomwake_in (txcomwake_in ),
+ .txctrl0_in (txctrl0_in ),
+ .txctrl1_in (txctrl1_in ),
+ .txctrl2_in (txctrl2_in ),
+ .txdata_in (txdata_in ),
+ .txdataextendrsvd_in (txdataextendrsvd_in ),
+ .txdccforcestart_in (txdccforcestart_in ),
+ .txdccreset_in (txdccreset_in ),
+ .txdeemph_in (txdeemph_in ),
+ .txdetectrx_in (txdetectrx_in ),
+ .txdiffctrl_in (txdiffctrl_in ),
+ .txdlybypass_in (txdlybypass_in ),
+ .txdlyen_in (txdlyen_in ),
+ .txdlyhold_in (txdlyhold_in ),
+ .txdlyovrden_in (txdlyovrden_in ),
+ .txdlysreset_in (txdlysreset_in ),
+ .txdlyupdown_in (txdlyupdown_in ),
+ .txelecidle_in (txelecidle_in ),
+ .txheader_in (txheader_in ),
+ .txinhibit_in (txinhibit_in ),
+ .txlatclk_in (txlatclk_in ),
+ .txlfpstreset_in (txlfpstreset_in ),
+ .txlfpsu2lpexit_in (txlfpsu2lpexit_in ),
+ .txlfpsu3wake_in (txlfpsu3wake_in ),
+ .txmaincursor_in (txmaincursor_in ),
+ .txmargin_in (txmargin_in ),
+ .txmuxdcdexhold_in (txmuxdcdexhold_in ),
+ .txmuxdcdorwren_in (txmuxdcdorwren_in ),
+ .txoneszeros_in (txoneszeros_in ),
+ .txoutclksel_in (txoutclksel_in ),
+ .txpcsreset_in (txpcsreset_in ),
+ .txpd_in (txpd_in ),
+ .txpdelecidlemode_in (txpdelecidlemode_in ),
+ .txphalign_in (txphalign_in ),
+ .txphalignen_in (txphalignen_in ),
+ .txphdlypd_in (txphdlypd_in ),
+ .txphdlyreset_in (txphdlyreset_in ),
+ .txphdlytstclk_in (txphdlytstclk_in ),
+ .txphinit_in (txphinit_in ),
+ .txphovrden_in (txphovrden_in ),
+ .txpippmen_in (txpippmen_in ),
+ .txpippmovrden_in (txpippmovrden_in ),
+ .txpippmpd_in (txpippmpd_in ),
+ .txpippmsel_in (txpippmsel_in ),
+ .txpippmstepsize_in (txpippmstepsize_in ),
+ .txpisopd_in (txpisopd_in ),
+ .txpllclksel_in (txpllclksel_in ),
+ .txpmareset_in (txpmareset_in ),
+ .txpolarity_in (txpolarity_in ),
+ .txpostcursor_in (txpostcursor_in ),
+ .txprbsforceerr_in (txprbsforceerr_in ),
+ .txprbssel_in (txprbssel_in ),
+ .txprecursor_in (txprecursor_in ),
+ .txprogdivreset_in (txprogdivreset_in ),
+ .txqpibiasen_in (txqpibiasen_in ),
+ .txqpiweakpup_in (txqpiweakpup_in ),
+ .txrate_in (txrate_in ),
+ .txratemode_in (txratemode_in ),
+ .txsequence_in (txsequence_in ),
+ .txswing_in (txswing_in ),
+ .txsyncallin_in (txsyncallin_in ),
+ .txsyncin_in (txsyncin_in ),
+ .txsyncmode_in (txsyncmode_in ),
+ .txsysclksel_in (txsysclksel_in ),
+ .txuserrdy_in (txuserrdy_in ),
+ .txusrclk_in (txusrclk_in ),
+ .txusrclk2_in (txusrclk2_in ),
+ .bufgtce_out (bufgtce_out ),
+ .bufgtcemask_out (bufgtcemask_out ),
+ .bufgtdiv_out (bufgtdiv_out ),
+ .bufgtreset_out (bufgtreset_out ),
+ .bufgtrstmask_out (bufgtrstmask_out ),
+ .cpllfbclklost_out (cpllfbclklost_out ),
+ .cplllock_out (cplllock_out ),
+ .cpllrefclklost_out (cpllrefclklost_out ),
+ .dmonitorout_out (dmonitorout_out ),
+ .dmonitoroutclk_out (dmonitoroutclk_out ),
+ .drpdo_out (drpdo_out ),
+ .drprdy_out (drprdy_out ),
+ .eyescandataerror_out (eyescandataerror_out ),
+ .gthtxn_out (gthtxn_out ),
+ .gthtxp_out (gthtxp_out ),
+ .gtpowergood_out (gtpowergood_out ),
+ .gtrefclkmonitor_out (gtrefclkmonitor_out ),
+ .pcierategen3_out (pcierategen3_out ),
+ .pcierateidle_out (pcierateidle_out ),
+ .pcierateqpllpd_out (pcierateqpllpd_out ),
+ .pcierateqpllreset_out (pcierateqpllreset_out ),
+ .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
+ .pcieusergen3rdy_out (pcieusergen3rdy_out ),
+ .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
+ .pcieuserratestart_out (pcieuserratestart_out ),
+ .pcsrsvdout_out (pcsrsvdout_out ),
+ .phystatus_out (phystatus_out ),
+ .pinrsrvdas_out (pinrsrvdas_out ),
+ .powerpresent_out (powerpresent_out ),
+ .resetexception_out (resetexception_out ),
+ .rxbufstatus_out (rxbufstatus_out ),
+ .rxbyteisaligned_out (rxbyteisaligned_out ),
+ .rxbyterealign_out (rxbyterealign_out ),
+ .rxcdrlock_out (rxcdrlock_out ),
+ .rxcdrphdone_out (rxcdrphdone_out ),
+ .rxchanbondseq_out (rxchanbondseq_out ),
+ .rxchanisaligned_out (rxchanisaligned_out ),
+ .rxchanrealign_out (rxchanrealign_out ),
+ .rxchbondo_out (rxchbondo_out ),
+ .rxckcaldone_out (rxckcaldone_out ),
+ .rxclkcorcnt_out (rxclkcorcnt_out ),
+ .rxcominitdet_out (rxcominitdet_out ),
+ .rxcommadet_out (rxcommadet_out ),
+ .rxcomsasdet_out (rxcomsasdet_out ),
+ .rxcomwakedet_out (rxcomwakedet_out ),
+ .rxctrl0_out (rxctrl0_out ),
+ .rxctrl1_out (rxctrl1_out ),
+ .rxctrl2_out (rxctrl2_out ),
+ .rxctrl3_out (rxctrl3_out ),
+ .rxdata_out (rxdata_out ),
+ .rxdataextendrsvd_out (rxdataextendrsvd_out ),
+ .rxdatavalid_out (rxdatavalid_out ),
+ .rxdlysresetdone_out (rxdlysresetdone_out ),
+ .rxelecidle_out (rxelecidle_out ),
+ .rxheader_out (rxheader_out ),
+ .rxheadervalid_out (rxheadervalid_out ),
+ .rxlfpstresetdet_out (rxlfpstresetdet_out ),
+ .rxlfpsu2lpexitdet_out (rxlfpsu2lpexitdet_out ),
+ .rxlfpsu3wakedet_out (rxlfpsu3wakedet_out ),
+ .rxmonitorout_out (rxmonitorout_out ),
+ .rxosintdone_out (rxosintdone_out ),
+ .rxosintstarted_out (rxosintstarted_out ),
+ .rxosintstrobedone_out (rxosintstrobedone_out ),
+ .rxosintstrobestarted_out (rxosintstrobestarted_out ),
+ .rxoutclk_out (rxoutclk_out ),
+ .rxoutclkfabric_out (rxoutclkfabric_out ),
+ .rxoutclkpcs_out (rxoutclkpcs_out ),
+ .rxphaligndone_out (rxphaligndone_out ),
+ .rxphalignerr_out (rxphalignerr_out ),
+ .rxpmaresetdone_out (rxpmaresetdone_out ),
+ .rxprbserr_out (rxprbserr_out ),
+ .rxprbslocked_out (rxprbslocked_out ),
+ .rxprgdivresetdone_out (rxprgdivresetdone_out ),
+ .rxqpisenn_out (rxqpisenn_out ),
+ .rxqpisenp_out (rxqpisenp_out ),
+ .rxratedone_out (rxratedone_out ),
+ .rxrecclkout_out (rxrecclkout_out ),
+ .rxresetdone_out (rxresetdone_out ),
+ .rxsliderdy_out (rxsliderdy_out ),
+ .rxslipdone_out (rxslipdone_out ),
+ .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
+ .rxslippmardy_out (rxslippmardy_out ),
+ .rxstartofseq_out (rxstartofseq_out ),
+ .rxstatus_out (rxstatus_out ),
+ .rxsyncdone_out (rxsyncdone_out ),
+ .rxsyncout_out (rxsyncout_out ),
+ .rxvalid_out (rxvalid_out ),
+ .txbufstatus_out (txbufstatus_out ),
+ .txcomfinish_out (txcomfinish_out ),
+ .txdccdone_out (txdccdone_out ),
+ .txdlysresetdone_out (txdlysresetdone_out ),
+ .txoutclk_out (txoutclk_out ),
+ .txoutclkfabric_out (txoutclkfabric_out ),
+ .txoutclkpcs_out (txoutclkpcs_out ),
+ .txphaligndone_out (txphaligndone_out ),
+ .txphinitdone_out (txphinitdone_out ),
+ .txpmaresetdone_out (txpmaresetdone_out ),
+ .txprgdivresetdone_out (txprgdivresetdone_out ),
+ .txqpisenn_out (txqpisenn_out ),
+ .txqpisenp_out (txqpisenp_out ),
+ .txratedone_out (txratedone_out ),
+ .txresetdone_out (txresetdone_out ),
+ .txsyncdone_out (txsyncdone_out ),
+ .txsyncout_out (txsyncout_out )
+ );
-// // Generate GTYE3-type Transceivers Wizard submodule
-// gtwizard_ultrascale_2_gtwizard_gtye3 #(
-// .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
-// .C_PCIE_ENABLE (C_PCIE_ENABLE ),
-// .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
-// .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
-// .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
-// .C_GT_REV (C_GT_REV ),
-// .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
-// .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
-// .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
-// .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
-// .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
-// .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
-// .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
-// .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
-// .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
-// .C_RX_ENABLE (C_RX_ENABLE ),
-// .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
-// .C_RX_LINE_RATE (C_RX_LINE_RATE ),
-// .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
-// .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
-// .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
-// .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
-// .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
-// .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
-// .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
-// .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
-// .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
-// .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
-// .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
-// .C_TX_ENABLE (C_TX_ENABLE ),
-// .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
-// .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
-// .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
-// .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
-// .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
-// .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
-// .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
-// ) gtwizard_ultrascale_2_gtwizard_gtye3_inst (
-// .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
-// .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
-// .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
-// .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
-// .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
-// .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
-// .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
-// .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
-// .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
-// .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
-// .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
-// .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
-// .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
-// .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
-// .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
-// .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
-// .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
-// .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
-// .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
-// .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
-// .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
-// .gtwiz_reset_all_in (gtwiz_reset_all_in ),
-// .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in),
-// .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
-// .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in),
-// .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
-// .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
-// .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
-// .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
-// .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
-// .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
-// .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
-// .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
-// .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
-// .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
-// .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
-// .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
-// .bgbypassb_in (bgbypassb_in ),
-// .bgmonitorenb_in (bgmonitorenb_in ),
-// .bgpdb_in (bgpdb_in ),
-// .bgrcalovrd_in (bgrcalovrd_in ),
-// .bgrcalovrdenb_in (bgrcalovrdenb_in ),
-// .drpaddr_common_in (drpaddr_common_in ),
-// .drpclk_common_in (drpclk_common_in ),
-// .drpdi_common_in (drpdi_common_in ),
-// .drpen_common_in (drpen_common_in ),
-// .drpwe_common_in (drpwe_common_in ),
-// .gtgrefclk0_in (gtgrefclk0_in ),
-// .gtgrefclk1_in (gtgrefclk1_in ),
-// .gtnorthrefclk00_in (gtnorthrefclk00_in ),
-// .gtnorthrefclk01_in (gtnorthrefclk01_in ),
-// .gtnorthrefclk10_in (gtnorthrefclk10_in ),
-// .gtnorthrefclk11_in (gtnorthrefclk11_in ),
-// .gtrefclk00_in (gtrefclk00_in ),
-// .gtrefclk01_in (gtrefclk01_in ),
-// .gtrefclk10_in (gtrefclk10_in ),
-// .gtrefclk11_in (gtrefclk11_in ),
-// .gtsouthrefclk00_in (gtsouthrefclk00_in ),
-// .gtsouthrefclk01_in (gtsouthrefclk01_in ),
-// .gtsouthrefclk10_in (gtsouthrefclk10_in ),
-// .gtsouthrefclk11_in (gtsouthrefclk11_in ),
-// .pmarsvd0_in (pmarsvd0_in ),
-// .pmarsvd1_in (pmarsvd1_in ),
-// .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
-// .qpll0lockdetclk_in (qpll0lockdetclk_in ),
-// .qpll0locken_in (qpll0locken_in ),
-// .qpll0pd_in (qpll0pd_in ),
-// .qpll0refclksel_in (qpll0refclksel_in ),
-// .qpll0reset_in (qpll0reset_in ),
-// .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
-// .qpll1lockdetclk_in (qpll1lockdetclk_in ),
-// .qpll1locken_in (qpll1locken_in ),
-// .qpll1pd_in (qpll1pd_in ),
-// .qpll1refclksel_in (qpll1refclksel_in ),
-// .qpll1reset_in (qpll1reset_in ),
-// .qpllrsvd1_in (qpllrsvd1_in ),
-// .qpllrsvd2_in (qpllrsvd2_in ),
-// .qpllrsvd3_in (qpllrsvd3_in ),
-// .qpllrsvd4_in (qpllrsvd4_in ),
-// .rcalenb_in (rcalenb_in ),
-// .sdm0data_in (sdm0data_in ),
-// .sdm0reset_in (sdm0reset_in ),
-// .sdm0width_in (sdm0width_in ),
-// .sdm1data_in (sdm1data_in ),
-// .sdm1reset_in (sdm1reset_in ),
-// .sdm1width_in (sdm1width_in ),
-// .drpdo_common_out (drpdo_common_out ),
-// .drprdy_common_out (drprdy_common_out ),
-// .pmarsvdout0_out (pmarsvdout0_out ),
-// .pmarsvdout1_out (pmarsvdout1_out ),
-// .qpll0fbclklost_out (qpll0fbclklost_out ),
-// .qpll0lock_out (qpll0lock_out ),
-// .qpll0outclk_out (qpll0outclk_out ),
-// .qpll0outrefclk_out (qpll0outrefclk_out ),
-// .qpll0refclklost_out (qpll0refclklost_out ),
-// .qpll1fbclklost_out (qpll1fbclklost_out ),
-// .qpll1lock_out (qpll1lock_out ),
-// .qpll1outclk_out (qpll1outclk_out ),
-// .qpll1outrefclk_out (qpll1outrefclk_out ),
-// .qpll1refclklost_out (qpll1refclklost_out ),
-// .qplldmonitor0_out (qplldmonitor0_out ),
-// .qplldmonitor1_out (qplldmonitor1_out ),
-// .refclkoutmonitor0_out (refclkoutmonitor0_out ),
-// .refclkoutmonitor1_out (refclkoutmonitor1_out ),
-// .rxrecclk0_sel_out (rxrecclk0_sel_out ),
-// .rxrecclk1_sel_out (rxrecclk1_sel_out ),
-// .sdm0finalout_out (sdm0finalout_out ),
-// .sdm0testdata_out (sdm0testdata_out ),
-// .sdm1finalout_out (sdm1finalout_out ),
-// .sdm1testdata_out (sdm1testdata_out ),
-// .cdrstepdir_in (cdrstepdir_in ),
-// .cdrstepsq_in (cdrstepsq_in ),
-// .cdrstepsx_in (cdrstepsx_in ),
-// .cfgreset_in (cfgreset_in ),
-// .clkrsvd0_in (clkrsvd0_in ),
-// .clkrsvd1_in (clkrsvd1_in ),
-// .cplllockdetclk_in (cplllockdetclk_in ),
-// .cplllocken_in (cplllocken_in ),
-// .cpllpd_in (cpllpd_in ),
-// .cpllrefclksel_in (cpllrefclksel_in ),
-// .cpllreset_in (cpllreset_in ),
-// .dmonfiforeset_in (dmonfiforeset_in ),
-// .dmonitorclk_in (dmonitorclk_in ),
-// .drpaddr_in (drpaddr_in ),
-// .drpclk_in (drpclk_in ),
-// .drpdi_in (drpdi_in ),
-// .drpen_in (drpen_in ),
-// .drpwe_in (drpwe_in ),
-// .elpcaldvorwren_in (elpcaldvorwren_in ),
-// .elpcalpaorwren_in (elpcalpaorwren_in ),
-// .evoddphicaldone_in (evoddphicaldone_in ),
-// .evoddphicalstart_in (evoddphicalstart_in ),
-// .evoddphidrden_in (evoddphidrden_in ),
-// .evoddphidwren_in (evoddphidwren_in ),
-// .evoddphixrden_in (evoddphixrden_in ),
-// .evoddphixwren_in (evoddphixwren_in ),
-// .eyescanmode_in (eyescanmode_in ),
-// .eyescanreset_in (eyescanreset_in ),
-// .eyescantrigger_in (eyescantrigger_in ),
-// .gtgrefclk_in (gtgrefclk_in ),
-// .gtnorthrefclk0_in (gtnorthrefclk0_in ),
-// .gtnorthrefclk1_in (gtnorthrefclk1_in ),
-// .gtrefclk0_in (gtrefclk0_in ),
-// .gtrefclk1_in (gtrefclk1_in ),
-// .gtresetsel_in (gtresetsel_in ),
-// .gtrsvd_in (gtrsvd_in ),
-// .gtrxreset_in (gtrxreset_in ),
-// .gtsouthrefclk0_in (gtsouthrefclk0_in ),
-// .gtsouthrefclk1_in (gtsouthrefclk1_in ),
-// .gttxreset_in (gttxreset_in ),
-// .gtyrxn_in (gtyrxn_in ),
-// .gtyrxp_in (gtyrxp_in ),
-// .loopback_in (loopback_in ),
-// .looprsvd_in (looprsvd_in ),
-// .lpbkrxtxseren_in (lpbkrxtxseren_in ),
-// .lpbktxrxseren_in (lpbktxrxseren_in ),
-// .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
-// .pcierstidle_in (pcierstidle_in ),
-// .pciersttxsyncstart_in (pciersttxsyncstart_in ),
-// .pcieuserratedone_in (pcieuserratedone_in ),
-// .pcsrsvdin_in (pcsrsvdin_in ),
-// .pcsrsvdin2_in (pcsrsvdin2_in ),
-// .pmarsvdin_in (pmarsvdin_in ),
-// .qpll0clk_in (qpll0clk_in ),
-// .qpll0refclk_in (qpll0refclk_in ),
-// .qpll1clk_in (qpll1clk_in ),
-// .qpll1refclk_in (qpll1refclk_in ),
-// .resetovrd_in (resetovrd_in ),
-// .rstclkentx_in (rstclkentx_in ),
-// .rx8b10ben_in (rx8b10ben_in ),
-// .rxbufreset_in (rxbufreset_in ),
-// .rxcdrfreqreset_in (rxcdrfreqreset_in ),
-// .rxcdrhold_in (rxcdrhold_in ),
-// .rxcdrovrden_in (rxcdrovrden_in ),
-// .rxcdrreset_in (rxcdrreset_in ),
-// .rxcdrresetrsv_in (rxcdrresetrsv_in ),
-// .rxchbonden_in (rxchbonden_in ),
-// .rxchbondi_in (rxchbondi_in ),
-// .rxchbondlevel_in (rxchbondlevel_in ),
-// .rxchbondmaster_in (rxchbondmaster_in ),
-// .rxchbondslave_in (rxchbondslave_in ),
-// .rxckcalreset_in (rxckcalreset_in ),
-// .rxcommadeten_in (rxcommadeten_in ),
-// .rxdccforcestart_in (rxdccforcestart_in ),
-// .rxdfeagchold_in (rxdfeagchold_in ),
-// .rxdfeagcovrden_in (rxdfeagcovrden_in ),
-// .rxdfelfhold_in (rxdfelfhold_in ),
-// .rxdfelfovrden_in (rxdfelfovrden_in ),
-// .rxdfelpmreset_in (rxdfelpmreset_in ),
-// .rxdfetap10hold_in (rxdfetap10hold_in ),
-// .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
-// .rxdfetap11hold_in (rxdfetap11hold_in ),
-// .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
-// .rxdfetap12hold_in (rxdfetap12hold_in ),
-// .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
-// .rxdfetap13hold_in (rxdfetap13hold_in ),
-// .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
-// .rxdfetap14hold_in (rxdfetap14hold_in ),
-// .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
-// .rxdfetap15hold_in (rxdfetap15hold_in ),
-// .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
-// .rxdfetap2hold_in (rxdfetap2hold_in ),
-// .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
-// .rxdfetap3hold_in (rxdfetap3hold_in ),
-// .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
-// .rxdfetap4hold_in (rxdfetap4hold_in ),
-// .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
-// .rxdfetap5hold_in (rxdfetap5hold_in ),
-// .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
-// .rxdfetap6hold_in (rxdfetap6hold_in ),
-// .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
-// .rxdfetap7hold_in (rxdfetap7hold_in ),
-// .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
-// .rxdfetap8hold_in (rxdfetap8hold_in ),
-// .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
-// .rxdfetap9hold_in (rxdfetap9hold_in ),
-// .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
-// .rxdfeuthold_in (rxdfeuthold_in ),
-// .rxdfeutovrden_in (rxdfeutovrden_in ),
-// .rxdfevphold_in (rxdfevphold_in ),
-// .rxdfevpovrden_in (rxdfevpovrden_in ),
-// .rxdfevsen_in (rxdfevsen_in ),
-// .rxdfexyden_in (rxdfexyden_in ),
-// .rxdlybypass_in (rxdlybypass_in ),
-// .rxdlyen_in (rxdlyen_in ),
-// .rxdlyovrden_in (rxdlyovrden_in ),
-// .rxdlysreset_in (rxdlysreset_in ),
-// .rxelecidlemode_in (rxelecidlemode_in ),
-// .rxgearboxslip_in (rxgearboxslip_in ),
-// .rxlatclk_in (rxlatclk_in ),
-// .rxlpmen_in (rxlpmen_in ),
-// .rxlpmgchold_in (rxlpmgchold_in ),
-// .rxlpmgcovrden_in (rxlpmgcovrden_in ),
-// .rxlpmhfhold_in (rxlpmhfhold_in ),
-// .rxlpmhfovrden_in (rxlpmhfovrden_in ),
-// .rxlpmlfhold_in (rxlpmlfhold_in ),
-// .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
-// .rxlpmoshold_in (rxlpmoshold_in ),
-// .rxlpmosovrden_in (rxlpmosovrden_in ),
-// .rxmcommaalignen_in (rxmcommaalignen_in ),
-// .rxmonitorsel_in (rxmonitorsel_in ),
-// .rxoobreset_in (rxoobreset_in ),
-// .rxoscalreset_in (rxoscalreset_in ),
-// .rxoshold_in (rxoshold_in ),
-// .rxosintcfg_in (rxosintcfg_in ),
-// .rxosinten_in (rxosinten_in ),
-// .rxosinthold_in (rxosinthold_in ),
-// .rxosintovrden_in (rxosintovrden_in ),
-// .rxosintstrobe_in (rxosintstrobe_in ),
-// .rxosinttestovrden_in (rxosinttestovrden_in ),
-// .rxosovrden_in (rxosovrden_in ),
-// .rxoutclksel_in (rxoutclksel_in ),
-// .rxpcommaalignen_in (rxpcommaalignen_in ),
-// .rxpcsreset_in (rxpcsreset_in ),
-// .rxpd_in (rxpd_in ),
-// .rxphalign_in (rxphalign_in ),
-// .rxphalignen_in (rxphalignen_in ),
-// .rxphdlypd_in (rxphdlypd_in ),
-// .rxphdlyreset_in (rxphdlyreset_in ),
-// .rxphovrden_in (rxphovrden_in ),
-// .rxpllclksel_in (rxpllclksel_in ),
-// .rxpmareset_in (rxpmareset_in ),
-// .rxpolarity_in (rxpolarity_in ),
-// .rxprbscntreset_in (rxprbscntreset_in ),
-// .rxprbssel_in (rxprbssel_in ),
-// .rxprogdivreset_in (rxprogdivreset_in ),
-// .rxrate_in (rxrate_in ),
-// .rxratemode_in (rxratemode_in ),
-// .rxslide_in (rxslide_in ),
-// .rxslipoutclk_in (rxslipoutclk_in ),
-// .rxslippma_in (rxslippma_in ),
-// .rxsyncallin_in (rxsyncallin_in ),
-// .rxsyncin_in (rxsyncin_in ),
-// .rxsyncmode_in (rxsyncmode_in ),
-// .rxsysclksel_in (rxsysclksel_in ),
-// .rxuserrdy_in (rxuserrdy_in ),
-// .rxusrclk_in (rxusrclk_in ),
-// .rxusrclk2_in (rxusrclk2_in ),
-// .sigvalidclk_in (sigvalidclk_in ),
-// .tstin_in (tstin_in ),
-// .tx8b10bbypass_in (tx8b10bbypass_in ),
-// .tx8b10ben_in (tx8b10ben_in ),
-// .txbufdiffctrl_in (txbufdiffctrl_in ),
-// .txcominit_in (txcominit_in ),
-// .txcomsas_in (txcomsas_in ),
-// .txcomwake_in (txcomwake_in ),
-// .txctrl0_in (txctrl0_in ),
-// .txctrl1_in (txctrl1_in ),
-// .txctrl2_in (txctrl2_in ),
-// .txdata_in (txdata_in ),
-// .txdataextendrsvd_in (txdataextendrsvd_in ),
-// .txdccforcestart_in (txdccforcestart_in ),
-// .txdccreset_in (txdccreset_in ),
-// .txdeemph_in (txdeemph_in ),
-// .txdetectrx_in (txdetectrx_in ),
-// .txdiffctrl_in (txdiffctrl_in ),
-// .txdiffpd_in (txdiffpd_in ),
-// .txdlybypass_in (txdlybypass_in ),
-// .txdlyen_in (txdlyen_in ),
-// .txdlyhold_in (txdlyhold_in ),
-// .txdlyovrden_in (txdlyovrden_in ),
-// .txdlysreset_in (txdlysreset_in ),
-// .txdlyupdown_in (txdlyupdown_in ),
-// .txelecidle_in (txelecidle_in ),
-// .txelforcestart_in (txelforcestart_in ),
-// .txheader_in (txheader_in ),
-// .txinhibit_in (txinhibit_in ),
-// .txlatclk_in (txlatclk_in ),
-// .txmaincursor_in (txmaincursor_in ),
-// .txmargin_in (txmargin_in ),
-// .txoutclksel_in (txoutclksel_in ),
-// .txpcsreset_in (txpcsreset_in ),
-// .txpd_in (txpd_in ),
-// .txpdelecidlemode_in (txpdelecidlemode_in ),
-// .txphalign_in (txphalign_in ),
-// .txphalignen_in (txphalignen_in ),
-// .txphdlypd_in (txphdlypd_in ),
-// .txphdlyreset_in (txphdlyreset_in ),
-// .txphdlytstclk_in (txphdlytstclk_in ),
-// .txphinit_in (txphinit_in ),
-// .txphovrden_in (txphovrden_in ),
-// .txpippmen_in (txpippmen_in ),
-// .txpippmovrden_in (txpippmovrden_in ),
-// .txpippmpd_in (txpippmpd_in ),
-// .txpippmsel_in (txpippmsel_in ),
-// .txpippmstepsize_in (txpippmstepsize_in ),
-// .txpisopd_in (txpisopd_in ),
-// .txpllclksel_in (txpllclksel_in ),
-// .txpmareset_in (txpmareset_in ),
-// .txpolarity_in (txpolarity_in ),
-// .txpostcursor_in (txpostcursor_in ),
-// .txprbsforceerr_in (txprbsforceerr_in ),
-// .txprbssel_in (txprbssel_in ),
-// .txprecursor_in (txprecursor_in ),
-// .txprogdivreset_in (txprogdivreset_in ),
-// .txrate_in (txrate_in ),
-// .txratemode_in (txratemode_in ),
-// .txsequence_in (txsequence_in ),
-// .txswing_in (txswing_in ),
-// .txsyncallin_in (txsyncallin_in ),
-// .txsyncin_in (txsyncin_in ),
-// .txsyncmode_in (txsyncmode_in ),
-// .txsysclksel_in (txsysclksel_in ),
-// .txuserrdy_in (txuserrdy_in ),
-// .txusrclk_in (txusrclk_in ),
-// .txusrclk2_in (txusrclk2_in ),
-// .bufgtce_out (bufgtce_out ),
-// .bufgtcemask_out (bufgtcemask_out ),
-// .bufgtdiv_out (bufgtdiv_out ),
-// .bufgtreset_out (bufgtreset_out ),
-// .bufgtrstmask_out (bufgtrstmask_out ),
-// .cpllfbclklost_out (cpllfbclklost_out ),
-// .cplllock_out (cplllock_out ),
-// .cpllrefclklost_out (cpllrefclklost_out ),
-// .dmonitorout_out (dmonitorout_out ),
-// .drpdo_out (drpdo_out ),
-// .drprdy_out (drprdy_out ),
-// .eyescandataerror_out (eyescandataerror_out ),
-// .gtpowergood_out (gtpowergood_out ),
-// .gtrefclkmonitor_out (gtrefclkmonitor_out ),
-// .gtytxn_out (gtytxn_out ),
-// .gtytxp_out (gtytxp_out ),
-// .pcierategen3_out (pcierategen3_out ),
-// .pcierateidle_out (pcierateidle_out ),
-// .pcierateqpllpd_out (pcierateqpllpd_out ),
-// .pcierateqpllreset_out (pcierateqpllreset_out ),
-// .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
-// .pcieusergen3rdy_out (pcieusergen3rdy_out ),
-// .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
-// .pcieuserratestart_out (pcieuserratestart_out ),
-// .pcsrsvdout_out (pcsrsvdout_out ),
-// .phystatus_out (phystatus_out ),
-// .pinrsrvdas_out (pinrsrvdas_out ),
-// .resetexception_out (resetexception_out ),
-// .rxbufstatus_out (rxbufstatus_out ),
-// .rxbyteisaligned_out (rxbyteisaligned_out ),
-// .rxbyterealign_out (rxbyterealign_out ),
-// .rxcdrlock_out (rxcdrlock_out ),
-// .rxcdrphdone_out (rxcdrphdone_out ),
-// .rxchanbondseq_out (rxchanbondseq_out ),
-// .rxchanisaligned_out (rxchanisaligned_out ),
-// .rxchanrealign_out (rxchanrealign_out ),
-// .rxchbondo_out (rxchbondo_out ),
-// .rxckcaldone_out (rxckcaldone_out ),
-// .rxclkcorcnt_out (rxclkcorcnt_out ),
-// .rxcominitdet_out (rxcominitdet_out ),
-// .rxcommadet_out (rxcommadet_out ),
-// .rxcomsasdet_out (rxcomsasdet_out ),
-// .rxcomwakedet_out (rxcomwakedet_out ),
-// .rxctrl0_out (rxctrl0_out ),
-// .rxctrl1_out (rxctrl1_out ),
-// .rxctrl2_out (rxctrl2_out ),
-// .rxctrl3_out (rxctrl3_out ),
-// .rxdata_out (rxdata_out ),
-// .rxdataextendrsvd_out (rxdataextendrsvd_out ),
-// .rxdatavalid_out (rxdatavalid_out ),
-// .rxdlysresetdone_out (rxdlysresetdone_out ),
-// .rxelecidle_out (rxelecidle_out ),
-// .rxheader_out (rxheader_out ),
-// .rxheadervalid_out (rxheadervalid_out ),
-// .rxmonitorout_out (rxmonitorout_out ),
-// .rxosintdone_out (rxosintdone_out ),
-// .rxosintstarted_out (rxosintstarted_out ),
-// .rxosintstrobedone_out (rxosintstrobedone_out ),
-// .rxosintstrobestarted_out (rxosintstrobestarted_out ),
-// .rxoutclk_out (rxoutclk_out ),
-// .rxoutclkfabric_out (rxoutclkfabric_out ),
-// .rxoutclkpcs_out (rxoutclkpcs_out ),
-// .rxphaligndone_out (rxphaligndone_out ),
-// .rxphalignerr_out (rxphalignerr_out ),
-// .rxpmaresetdone_out (rxpmaresetdone_out ),
-// .rxprbserr_out (rxprbserr_out ),
-// .rxprbslocked_out (rxprbslocked_out ),
-// .rxprgdivresetdone_out (rxprgdivresetdone_out ),
-// .rxratedone_out (rxratedone_out ),
-// .rxrecclkout_out (rxrecclkout_out ),
-// .rxresetdone_out (rxresetdone_out ),
-// .rxsliderdy_out (rxsliderdy_out ),
-// .rxslipdone_out (rxslipdone_out ),
-// .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
-// .rxslippmardy_out (rxslippmardy_out ),
-// .rxstartofseq_out (rxstartofseq_out ),
-// .rxstatus_out (rxstatus_out ),
-// .rxsyncdone_out (rxsyncdone_out ),
-// .rxsyncout_out (rxsyncout_out ),
-// .rxvalid_out (rxvalid_out ),
-// .txbufstatus_out (txbufstatus_out ),
-// .txcomfinish_out (txcomfinish_out ),
-// .txdccdone_out (txdccdone_out ),
-// .txdlysresetdone_out (txdlysresetdone_out ),
-// .txoutclk_out (txoutclk_out ),
-// .txoutclkfabric_out (txoutclkfabric_out ),
-// .txoutclkpcs_out (txoutclkpcs_out ),
-// .txphaligndone_out (txphaligndone_out ),
-// .txphinitdone_out (txphinitdone_out ),
-// .txpmaresetdone_out (txpmaresetdone_out ),
-// .txprgdivresetdone_out (txprgdivresetdone_out ),
-// .txratedone_out (txratedone_out ),
-// .txresetdone_out (txresetdone_out ),
-// .txsyncdone_out (txsyncdone_out ),
-// .txsyncout_out (txsyncout_out )
-// );
-//
-// // Drive unused outputs to constant values
-// assign rxrecclk0sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign rxrecclk1sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign dmonitoroutclk_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign gthtxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign gthtxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign powerpresent_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpstresetdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpsu2lpexitdet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxlfpsu3wakedet_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign txqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign txqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ // Drive unused outputs to constant values
+ assign rxrecclk0_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign rxrecclk1_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign gtytxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gtytxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
end
- else if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTHE4) begin : gen_gtwizard_gthe4_top
-
- // Generate GTHE4-type Transceivers Wizard submodule
- gtwizard_ultrascale_2_gtwizard_gthe4 #(
+ else if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTYE4) begin : gen_gtwizard_gtye4_top
+/*
+ // Generate GTYE4-type Transceivers Wizard submodule
+ gtwizard_ultrascale_2_gtwizard_gtye4 #(
.C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
.C_PCIE_ENABLE (C_PCIE_ENABLE ),
.C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
@@ -2362,7 +2902,7 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
.C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
.C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
- ) gtwizard_ultrascale_2_gtwizard_gthe4_inst (
+ ) gtwizard_ultrascale_2_gtwizard_gtye4_inst (
.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
@@ -2398,9 +2938,9 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
.gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
.gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
- .gtwiz_gthe4_cpll_cal_txoutclk_period_in (gtwiz_gthe4_cpll_cal_txoutclk_period_in),
- .gtwiz_gthe4_cpll_cal_cnt_tol_in (gtwiz_gthe4_cpll_cal_cnt_tol_in ),
- .gtwiz_gthe4_cpll_cal_bufg_ce_in (gtwiz_gthe4_cpll_cal_bufg_ce_in ),
+ .gtwiz_gtye4_cpll_cal_txoutclk_period_in (gtwiz_gtye4_cpll_cal_txoutclk_period_in),
+ .gtwiz_gtye4_cpll_cal_cnt_tol_in (gtwiz_gtye4_cpll_cal_cnt_tol_in ),
+ .gtwiz_gtye4_cpll_cal_bufg_ce_in (gtwiz_gtye4_cpll_cal_bufg_ce_in ),
.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
.bgbypassb_in (bgbypassb_in ),
@@ -2460,10 +3000,22 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.sdm1reset_in (sdm1reset_in ),
.sdm1toggle_in (sdm1toggle_in ),
.sdm1width_in (sdm1width_in ),
- .tcongpi_in (tcongpi_in ),
- .tconpowerup_in (tconpowerup_in ),
- .tconreset_in (tconreset_in ),
- .tconrsvdin1_in (tconrsvdin1_in ),
+ .ubcfgstreamen_in (ubcfgstreamen_in ),
+ .ubdo_in (ubdo_in ),
+ .ubdrdy_in (ubdrdy_in ),
+ .ubenable_in (ubenable_in ),
+ .ubgpi_in (ubgpi_in ),
+ .ubintr_in (ubintr_in ),
+ .ubiolmbrst_in (ubiolmbrst_in ),
+ .ubmbrst_in (ubmbrst_in ),
+ .ubmdmcapture_in (ubmdmcapture_in ),
+ .ubmdmdbgrst_in (ubmdmdbgrst_in ),
+ .ubmdmdbgupdate_in (ubmdmdbgupdate_in ),
+ .ubmdmregen_in (ubmdmregen_in ),
+ .ubmdmshift_in (ubmdmshift_in ),
+ .ubmdmsysrst_in (ubmdmsysrst_in ),
+ .ubmdmtck_in (ubmdmtck_in ),
+ .ubmdmtdi_in (ubmdmtdi_in ),
.drpdo_common_out (drpdo_common_out ),
.drprdy_common_out (drprdy_common_out ),
.pmarsvdout0_out (pmarsvdout0_out ),
@@ -2488,8 +3040,13 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.sdm0testdata_out (sdm0testdata_out ),
.sdm1finalout_out (sdm1finalout_out ),
.sdm1testdata_out (sdm1testdata_out ),
- .tcongpo_out (tcongpo_out ),
- .tconrsvdout0_out (tconrsvdout0_out ),
+ .ubdaddr_out (ubdaddr_out ),
+ .ubden_out (ubden_out ),
+ .ubdi_out (ubdi_out ),
+ .ubdwe_out (ubdwe_out ),
+ .ubmdmtdo_out (ubmdmtdo_out ),
+ .ubrsvdout_out (ubrsvdout_out ),
+ .ubtxuart_out (ubtxuart_out ),
.cdrstepdir_in (cdrstepdir_in ),
.cdrstepsq_in (cdrstepsq_in ),
.cdrstepsx_in (cdrstepsx_in ),
@@ -2514,8 +3071,6 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.eyescantrigger_in (eyescantrigger_in ),
.freqos_in (freqos_in ),
.gtgrefclk_in (gtgrefclk_in ),
- .gthrxn_in (gthrxn_in ),
- .gthrxp_in (gthrxp_in ),
.gtnorthrefclk0_in (gtnorthrefclk0_in ),
.gtnorthrefclk1_in (gtnorthrefclk1_in ),
.gtrefclk0_in (gtrefclk0_in ),
@@ -2528,6 +3083,8 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.gttxreset_in (gttxreset_in ),
.gttxresetsel_in (gttxresetsel_in ),
.incpctrl_in (incpctrl_in ),
+ .gtyrxn_in (gtyrxn_in ),
+ .gtyrxp_in (gtyrxp_in ),
.loopback_in (loopback_in ),
.pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
.pcierstidle_in (pcierstidle_in ),
@@ -2556,7 +3113,6 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.rxckcalreset_in (rxckcalreset_in ),
.rxckcalstart_in (rxckcalstart_in ),
.rxcommadeten_in (rxcommadeten_in ),
- .rxdfeagcctrl_in (rxdfeagcctrl_in ),
.rxdfeagchold_in (rxdfeagchold_in ),
.rxdfeagcovrden_in (rxdfeagcovrden_in ),
.rxdfecfokfcnum_in (rxdfecfokfcnum_in ),
@@ -2633,14 +3189,12 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.rxphalignen_in (rxphalignen_in ),
.rxphdlypd_in (rxphdlypd_in ),
.rxphdlyreset_in (rxphdlyreset_in ),
- .rxphovrden_in (rxphovrden_in ),
.rxpllclksel_in (rxpllclksel_in ),
.rxpmareset_in (rxpmareset_in ),
.rxpolarity_in (rxpolarity_in ),
.rxprbscntreset_in (rxprbscntreset_in ),
.rxprbssel_in (rxprbssel_in ),
.rxprogdivreset_in (rxprogdivreset_in ),
- .rxqpien_in (rxqpien_in ),
.rxrate_in (rxrate_in ),
.rxratemode_in (rxratemode_in ),
.rxslide_in (rxslide_in ),
@@ -2714,8 +3268,6 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.txprbssel_in (txprbssel_in ),
.txprecursor_in (txprecursor_in ),
.txprogdivreset_in (txprogdivreset_in ),
- .txqpibiasen_in (txqpibiasen_in ),
- .txqpiweakpup_in (txqpiweakpup_in ),
.txrate_in (txrate_in ),
.txratemode_in (txratemode_in ),
.txsequence_in (txsequence_in ),
@@ -2740,10 +3292,10 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.drpdo_out (drpdo_out ),
.drprdy_out (drprdy_out ),
.eyescandataerror_out (eyescandataerror_out ),
- .gthtxn_out (gthtxn_out ),
- .gthtxp_out (gthtxp_out ),
.gtpowergood_out (gtpowergood_out ),
.gtrefclkmonitor_out (gtrefclkmonitor_out ),
+ .gtytxn_out (gtytxn_out ),
+ .gtytxp_out (gtytxp_out ),
.pcierategen3_out (pcierategen3_out ),
.pcierateidle_out (pcierateidle_out ),
.pcierateqpllpd_out (pcierateqpllpd_out ),
@@ -2800,8 +3352,6 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.rxprbserr_out (rxprbserr_out ),
.rxprbslocked_out (rxprbslocked_out ),
.rxprgdivresetdone_out (rxprgdivresetdone_out ),
- .rxqpisenn_out (rxqpisenn_out ),
- .rxqpisenp_out (rxqpisenp_out ),
.rxratedone_out (rxratedone_out ),
.rxrecclkout_out (rxrecclkout_out ),
.rxresetdone_out (rxresetdone_out ),
@@ -2825,8 +3375,6 @@ module gtwizard_ultrascale_2_gtwizard_top #(
.txphinitdone_out (txphinitdone_out ),
.txpmaresetdone_out (txpmaresetdone_out ),
.txprgdivresetdone_out (txprgdivresetdone_out ),
- .txqpisenn_out (txqpisenn_out ),
- .txqpisenp_out (txqpisenp_out ),
.txratedone_out (txratedone_out ),
.txresetdone_out (txresetdone_out ),
.txsyncdone_out (txsyncdone_out ),
@@ -2834,565 +3382,17 @@ module gtwizard_ultrascale_2_gtwizard_top #(
);
// Drive unused outputs to constant values
- assign rxrecclk0_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign rxrecclk1_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubdaddr_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubden_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubdi_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubdwe_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubmdmtdo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubrsvdout_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign ubtxuart_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
- assign gtytxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
- assign gtytxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-
- end
- else if (C_GT_TYPE == `gtwizard_ultrascale_2_GT_TYPE__GTYE4) begin : gen_gtwizard_gtye4_top
-
-// // Generate GTYE4-type Transceivers Wizard submodule
-// gtwizard_ultrascale_2_gtwizard_gtye4 #(
-// .C_CHANNEL_ENABLE (C_CHANNEL_ENABLE ),
-// .C_PCIE_ENABLE (C_PCIE_ENABLE ),
-// .C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
-// .C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
-// .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
-// .C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
-// .C_GT_REV (C_GT_REV ),
-// .C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
-// .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
-// .C_USER_GTPOWERGOOD_DELAY_EN (C_USER_GTPOWERGOOD_DELAY_EN ),
-// .C_SIM_CPLL_CAL_BYPASS (C_SIM_CPLL_CAL_BYPASS ),
-// .C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
-// .C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
-// .C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_RX_USER_CLOCKING (C_LOCATE_RX_USER_CLOCKING ),
-// .C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER ),
-// .C_LOCATE_TX_USER_CLOCKING (C_LOCATE_TX_USER_CLOCKING ),
-// .C_RESET_CONTROLLER_INSTANCE_CTRL (C_RESET_CONTROLLER_INSTANCE_CTRL ),
-// .C_RX_BUFFBYPASS_MODE (C_RX_BUFFBYPASS_MODE ),
-// .C_RX_BUFFER_BYPASS_INSTANCE_CTRL (C_RX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_RX_BUFFER_MODE (C_RX_BUFFER_MODE ),
-// .C_RX_DATA_DECODING (C_RX_DATA_DECODING ),
-// .C_RX_ENABLE (C_RX_ENABLE ),
-// .C_RX_INT_DATA_WIDTH (C_RX_INT_DATA_WIDTH ),
-// .C_RX_LINE_RATE (C_RX_LINE_RATE ),
-// .C_RX_MASTER_CHANNEL_IDX (C_RX_MASTER_CHANNEL_IDX ),
-// .C_RX_OUTCLK_BUFG_GT_DIV (C_RX_OUTCLK_BUFG_GT_DIV ),
-// .C_RX_PLL_TYPE (C_RX_PLL_TYPE ),
-// .C_RX_USER_CLOCKING_CONTENTS (C_RX_USER_CLOCKING_CONTENTS ),
-// .C_RX_USER_CLOCKING_INSTANCE_CTRL (C_RX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_RX_USER_CLOCKING_SOURCE (C_RX_USER_CLOCKING_SOURCE ),
-// .C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
-// .C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
-// .C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
-// .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
-// .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
-// .C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
-// .C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
-// .C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
-// .C_TX_DATA_ENCODING (C_TX_DATA_ENCODING ),
-// .C_TX_ENABLE (C_TX_ENABLE ),
-// .C_TX_INT_DATA_WIDTH (C_TX_INT_DATA_WIDTH ),
-// .C_TX_MASTER_CHANNEL_IDX (C_TX_MASTER_CHANNEL_IDX ),
-// .C_TX_OUTCLK_BUFG_GT_DIV (C_TX_OUTCLK_BUFG_GT_DIV ),
-// .C_TX_PLL_TYPE (C_TX_PLL_TYPE ),
-// .C_TX_USER_CLOCKING_CONTENTS (C_TX_USER_CLOCKING_CONTENTS ),
-// .C_TX_USER_CLOCKING_INSTANCE_CTRL (C_TX_USER_CLOCKING_INSTANCE_CTRL ),
-// .C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2),
-// .C_TX_USER_CLOCKING_SOURCE (C_TX_USER_CLOCKING_SOURCE ),
-// .C_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH )
-// ) gtwizard_ultrascale_2_gtwizard_gtye4_inst (
-// .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in ),
-// .gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_in ),
-// .gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out ),
-// .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out ),
-// .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out ),
-// .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),
-// .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in ),
-// .gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_in ),
-// .gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out ),
-// .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ),
-// .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out ),
-// .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ),
-// .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in ),
-// .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in ),
-// .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out ),
-// .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out ),
-// .gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in ),
-// .gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in ),
-// .gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out ),
-// .gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out ),
-// .gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
-// .gtwiz_reset_all_in (gtwiz_reset_all_in ),
-// .gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in),
-// .gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in ),
-// .gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in),
-// .gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in ),
-// .gtwiz_reset_tx_done_in (gtwiz_reset_tx_done_in ),
-// .gtwiz_reset_rx_done_in (gtwiz_reset_rx_done_in ),
-// .gtwiz_reset_qpll0lock_in (gtwiz_reset_qpll0lock_in ),
-// .gtwiz_reset_qpll1lock_in (gtwiz_reset_qpll1lock_in ),
-// .gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out ),
-// .gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out ),
-// .gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out ),
-// .gtwiz_reset_qpll0reset_out (gtwiz_reset_qpll0reset_out ),
-// .gtwiz_reset_qpll1reset_out (gtwiz_reset_qpll1reset_out ),
-// .gtwiz_gtye4_cpll_cal_txoutclk_period_in (gtwiz_gtye4_cpll_cal_txoutclk_period_in),
-// .gtwiz_gtye4_cpll_cal_cnt_tol_in (gtwiz_gtye4_cpll_cal_cnt_tol_in ),
-// .gtwiz_gtye4_cpll_cal_bufg_ce_in (gtwiz_gtye4_cpll_cal_bufg_ce_in ),
-// .gtwiz_userdata_tx_in (gtwiz_userdata_tx_in ),
-// .gtwiz_userdata_rx_out (gtwiz_userdata_rx_out ),
-// .bgbypassb_in (bgbypassb_in ),
-// .bgmonitorenb_in (bgmonitorenb_in ),
-// .bgpdb_in (bgpdb_in ),
-// .bgrcalovrd_in (bgrcalovrd_in ),
-// .bgrcalovrdenb_in (bgrcalovrdenb_in ),
-// .drpaddr_common_in (drpaddr_common_in ),
-// .drpclk_common_in (drpclk_common_in ),
-// .drpdi_common_in (drpdi_common_in ),
-// .drpen_common_in (drpen_common_in ),
-// .drpwe_common_in (drpwe_common_in ),
-// .gtgrefclk0_in (gtgrefclk0_in ),
-// .gtgrefclk1_in (gtgrefclk1_in ),
-// .gtnorthrefclk00_in (gtnorthrefclk00_in ),
-// .gtnorthrefclk01_in (gtnorthrefclk01_in ),
-// .gtnorthrefclk10_in (gtnorthrefclk10_in ),
-// .gtnorthrefclk11_in (gtnorthrefclk11_in ),
-// .gtrefclk00_in (gtrefclk00_in ),
-// .gtrefclk01_in (gtrefclk01_in ),
-// .gtrefclk10_in (gtrefclk10_in ),
-// .gtrefclk11_in (gtrefclk11_in ),
-// .gtsouthrefclk00_in (gtsouthrefclk00_in ),
-// .gtsouthrefclk01_in (gtsouthrefclk01_in ),
-// .gtsouthrefclk10_in (gtsouthrefclk10_in ),
-// .gtsouthrefclk11_in (gtsouthrefclk11_in ),
-// .pcierateqpll0_in (pcierateqpll0_in ),
-// .pcierateqpll1_in (pcierateqpll1_in ),
-// .pmarsvd0_in (pmarsvd0_in ),
-// .pmarsvd1_in (pmarsvd1_in ),
-// .qpll0clkrsvd0_in (qpll0clkrsvd0_in ),
-// .qpll0clkrsvd1_in (qpll0clkrsvd1_in ),
-// .qpll0fbdiv_in (qpll0fbdiv_in ),
-// .qpll0lockdetclk_in (qpll0lockdetclk_in ),
-// .qpll0locken_in (qpll0locken_in ),
-// .qpll0pd_in (qpll0pd_in ),
-// .qpll0refclksel_in (qpll0refclksel_in ),
-// .qpll0reset_in (qpll0reset_in ),
-// .qpll1clkrsvd0_in (qpll1clkrsvd0_in ),
-// .qpll1clkrsvd1_in (qpll1clkrsvd1_in ),
-// .qpll1fbdiv_in (qpll1fbdiv_in ),
-// .qpll1lockdetclk_in (qpll1lockdetclk_in ),
-// .qpll1locken_in (qpll1locken_in ),
-// .qpll1pd_in (qpll1pd_in ),
-// .qpll1refclksel_in (qpll1refclksel_in ),
-// .qpll1reset_in (qpll1reset_in ),
-// .qpllrsvd1_in (qpllrsvd1_in ),
-// .qpllrsvd2_in (qpllrsvd2_in ),
-// .qpllrsvd3_in (qpllrsvd3_in ),
-// .qpllrsvd4_in (qpllrsvd4_in ),
-// .rcalenb_in (rcalenb_in ),
-// .sdm0data_in (sdm0data_in ),
-// .sdm0reset_in (sdm0reset_in ),
-// .sdm0toggle_in (sdm0toggle_in ),
-// .sdm0width_in (sdm0width_in ),
-// .sdm1data_in (sdm1data_in ),
-// .sdm1reset_in (sdm1reset_in ),
-// .sdm1toggle_in (sdm1toggle_in ),
-// .sdm1width_in (sdm1width_in ),
-// .ubcfgstreamen_in (ubcfgstreamen_in ),
-// .ubdo_in (ubdo_in ),
-// .ubdrdy_in (ubdrdy_in ),
-// .ubenable_in (ubenable_in ),
-// .ubgpi_in (ubgpi_in ),
-// .ubintr_in (ubintr_in ),
-// .ubiolmbrst_in (ubiolmbrst_in ),
-// .ubmbrst_in (ubmbrst_in ),
-// .ubmdmcapture_in (ubmdmcapture_in ),
-// .ubmdmdbgrst_in (ubmdmdbgrst_in ),
-// .ubmdmdbgupdate_in (ubmdmdbgupdate_in ),
-// .ubmdmregen_in (ubmdmregen_in ),
-// .ubmdmshift_in (ubmdmshift_in ),
-// .ubmdmsysrst_in (ubmdmsysrst_in ),
-// .ubmdmtck_in (ubmdmtck_in ),
-// .ubmdmtdi_in (ubmdmtdi_in ),
-// .drpdo_common_out (drpdo_common_out ),
-// .drprdy_common_out (drprdy_common_out ),
-// .pmarsvdout0_out (pmarsvdout0_out ),
-// .pmarsvdout1_out (pmarsvdout1_out ),
-// .qpll0fbclklost_out (qpll0fbclklost_out ),
-// .qpll0lock_out (qpll0lock_out ),
-// .qpll0outclk_out (qpll0outclk_out ),
-// .qpll0outrefclk_out (qpll0outrefclk_out ),
-// .qpll0refclklost_out (qpll0refclklost_out ),
-// .qpll1fbclklost_out (qpll1fbclklost_out ),
-// .qpll1lock_out (qpll1lock_out ),
-// .qpll1outclk_out (qpll1outclk_out ),
-// .qpll1outrefclk_out (qpll1outrefclk_out ),
-// .qpll1refclklost_out (qpll1refclklost_out ),
-// .qplldmonitor0_out (qplldmonitor0_out ),
-// .qplldmonitor1_out (qplldmonitor1_out ),
-// .refclkoutmonitor0_out (refclkoutmonitor0_out ),
-// .refclkoutmonitor1_out (refclkoutmonitor1_out ),
-// .rxrecclk0sel_out (rxrecclk0sel_out ),
-// .rxrecclk1sel_out (rxrecclk1sel_out ),
-// .sdm0finalout_out (sdm0finalout_out ),
-// .sdm0testdata_out (sdm0testdata_out ),
-// .sdm1finalout_out (sdm1finalout_out ),
-// .sdm1testdata_out (sdm1testdata_out ),
-// .ubdaddr_out (ubdaddr_out ),
-// .ubden_out (ubden_out ),
-// .ubdi_out (ubdi_out ),
-// .ubdwe_out (ubdwe_out ),
-// .ubmdmtdo_out (ubmdmtdo_out ),
-// .ubrsvdout_out (ubrsvdout_out ),
-// .ubtxuart_out (ubtxuart_out ),
-// .cdrstepdir_in (cdrstepdir_in ),
-// .cdrstepsq_in (cdrstepsq_in ),
-// .cdrstepsx_in (cdrstepsx_in ),
-// .cfgreset_in (cfgreset_in ),
-// .clkrsvd0_in (clkrsvd0_in ),
-// .clkrsvd1_in (clkrsvd1_in ),
-// .cpllfreqlock_in (cpllfreqlock_in ),
-// .cplllockdetclk_in (cplllockdetclk_in ),
-// .cplllocken_in (cplllocken_in ),
-// .cpllpd_in (cpllpd_in ),
-// .cpllrefclksel_in (cpllrefclksel_in ),
-// .cpllreset_in (cpllreset_in ),
-// .dmonfiforeset_in (dmonfiforeset_in ),
-// .dmonitorclk_in (dmonitorclk_in ),
-// .drpaddr_in (drpaddr_in ),
-// .drpclk_in (drpclk_in ),
-// .drpdi_in (drpdi_in ),
-// .drpen_in (drpen_in ),
-// .drprst_in (drprst_in ),
-// .drpwe_in (drpwe_in ),
-// .eyescanreset_in (eyescanreset_in ),
-// .eyescantrigger_in (eyescantrigger_in ),
-// .freqos_in (freqos_in ),
-// .gtgrefclk_in (gtgrefclk_in ),
-// .gtnorthrefclk0_in (gtnorthrefclk0_in ),
-// .gtnorthrefclk1_in (gtnorthrefclk1_in ),
-// .gtrefclk0_in (gtrefclk0_in ),
-// .gtrefclk1_in (gtrefclk1_in ),
-// .gtrsvd_in (gtrsvd_in ),
-// .gtrxreset_in (gtrxreset_in ),
-// .gtrxresetsel_in (gtrxresetsel_in ),
-// .gtsouthrefclk0_in (gtsouthrefclk0_in ),
-// .gtsouthrefclk1_in (gtsouthrefclk1_in ),
-// .gttxreset_in (gttxreset_in ),
-// .gttxresetsel_in (gttxresetsel_in ),
-// .incpctrl_in (incpctrl_in ),
-// .gtyrxn_in (gtyrxn_in ),
-// .gtyrxp_in (gtyrxp_in ),
-// .loopback_in (loopback_in ),
-// .pcieeqrxeqadaptdone_in (pcieeqrxeqadaptdone_in ),
-// .pcierstidle_in (pcierstidle_in ),
-// .pciersttxsyncstart_in (pciersttxsyncstart_in ),
-// .pcieuserratedone_in (pcieuserratedone_in ),
-// .pcsrsvdin_in (pcsrsvdin_in ),
-// .qpll0clk_in (qpll0clk_in ),
-// .qpll0freqlock_in (qpll0freqlock_in ),
-// .qpll0refclk_in (qpll0refclk_in ),
-// .qpll1clk_in (qpll1clk_in ),
-// .qpll1freqlock_in (qpll1freqlock_in ),
-// .qpll1refclk_in (qpll1refclk_in ),
-// .resetovrd_in (resetovrd_in ),
-// .rx8b10ben_in (rx8b10ben_in ),
-// .rxafecfoken_in (rxafecfoken_in ),
-// .rxbufreset_in (rxbufreset_in ),
-// .rxcdrfreqreset_in (rxcdrfreqreset_in ),
-// .rxcdrhold_in (rxcdrhold_in ),
-// .rxcdrovrden_in (rxcdrovrden_in ),
-// .rxcdrreset_in (rxcdrreset_in ),
-// .rxchbonden_in (rxchbonden_in ),
-// .rxchbondi_in (rxchbondi_in ),
-// .rxchbondlevel_in (rxchbondlevel_in ),
-// .rxchbondmaster_in (rxchbondmaster_in ),
-// .rxchbondslave_in (rxchbondslave_in ),
-// .rxckcalreset_in (rxckcalreset_in ),
-// .rxckcalstart_in (rxckcalstart_in ),
-// .rxcommadeten_in (rxcommadeten_in ),
-// .rxdfeagchold_in (rxdfeagchold_in ),
-// .rxdfeagcovrden_in (rxdfeagcovrden_in ),
-// .rxdfecfokfcnum_in (rxdfecfokfcnum_in ),
-// .rxdfecfokfen_in (rxdfecfokfen_in ),
-// .rxdfecfokfpulse_in (rxdfecfokfpulse_in ),
-// .rxdfecfokhold_in (rxdfecfokhold_in ),
-// .rxdfecfokovren_in (rxdfecfokovren_in ),
-// .rxdfekhhold_in (rxdfekhhold_in ),
-// .rxdfekhovrden_in (rxdfekhovrden_in ),
-// .rxdfelfhold_in (rxdfelfhold_in ),
-// .rxdfelfovrden_in (rxdfelfovrden_in ),
-// .rxdfelpmreset_in (rxdfelpmreset_in ),
-// .rxdfetap10hold_in (rxdfetap10hold_in ),
-// .rxdfetap10ovrden_in (rxdfetap10ovrden_in ),
-// .rxdfetap11hold_in (rxdfetap11hold_in ),
-// .rxdfetap11ovrden_in (rxdfetap11ovrden_in ),
-// .rxdfetap12hold_in (rxdfetap12hold_in ),
-// .rxdfetap12ovrden_in (rxdfetap12ovrden_in ),
-// .rxdfetap13hold_in (rxdfetap13hold_in ),
-// .rxdfetap13ovrden_in (rxdfetap13ovrden_in ),
-// .rxdfetap14hold_in (rxdfetap14hold_in ),
-// .rxdfetap14ovrden_in (rxdfetap14ovrden_in ),
-// .rxdfetap15hold_in (rxdfetap15hold_in ),
-// .rxdfetap15ovrden_in (rxdfetap15ovrden_in ),
-// .rxdfetap2hold_in (rxdfetap2hold_in ),
-// .rxdfetap2ovrden_in (rxdfetap2ovrden_in ),
-// .rxdfetap3hold_in (rxdfetap3hold_in ),
-// .rxdfetap3ovrden_in (rxdfetap3ovrden_in ),
-// .rxdfetap4hold_in (rxdfetap4hold_in ),
-// .rxdfetap4ovrden_in (rxdfetap4ovrden_in ),
-// .rxdfetap5hold_in (rxdfetap5hold_in ),
-// .rxdfetap5ovrden_in (rxdfetap5ovrden_in ),
-// .rxdfetap6hold_in (rxdfetap6hold_in ),
-// .rxdfetap6ovrden_in (rxdfetap6ovrden_in ),
-// .rxdfetap7hold_in (rxdfetap7hold_in ),
-// .rxdfetap7ovrden_in (rxdfetap7ovrden_in ),
-// .rxdfetap8hold_in (rxdfetap8hold_in ),
-// .rxdfetap8ovrden_in (rxdfetap8ovrden_in ),
-// .rxdfetap9hold_in (rxdfetap9hold_in ),
-// .rxdfetap9ovrden_in (rxdfetap9ovrden_in ),
-// .rxdfeuthold_in (rxdfeuthold_in ),
-// .rxdfeutovrden_in (rxdfeutovrden_in ),
-// .rxdfevphold_in (rxdfevphold_in ),
-// .rxdfevpovrden_in (rxdfevpovrden_in ),
-// .rxdfexyden_in (rxdfexyden_in ),
-// .rxdlybypass_in (rxdlybypass_in ),
-// .rxdlyen_in (rxdlyen_in ),
-// .rxdlyovrden_in (rxdlyovrden_in ),
-// .rxdlysreset_in (rxdlysreset_in ),
-// .rxelecidlemode_in (rxelecidlemode_in ),
-// .rxeqtraining_in (rxeqtraining_in ),
-// .rxgearboxslip_in (rxgearboxslip_in ),
-// .rxlatclk_in (rxlatclk_in ),
-// .rxlpmen_in (rxlpmen_in ),
-// .rxlpmgchold_in (rxlpmgchold_in ),
-// .rxlpmgcovrden_in (rxlpmgcovrden_in ),
-// .rxlpmhfhold_in (rxlpmhfhold_in ),
-// .rxlpmhfovrden_in (rxlpmhfovrden_in ),
-// .rxlpmlfhold_in (rxlpmlfhold_in ),
-// .rxlpmlfklovrden_in (rxlpmlfklovrden_in ),
-// .rxlpmoshold_in (rxlpmoshold_in ),
-// .rxlpmosovrden_in (rxlpmosovrden_in ),
-// .rxmcommaalignen_in (rxmcommaalignen_in ),
-// .rxmonitorsel_in (rxmonitorsel_in ),
-// .rxoobreset_in (rxoobreset_in ),
-// .rxoscalreset_in (rxoscalreset_in ),
-// .rxoshold_in (rxoshold_in ),
-// .rxosovrden_in (rxosovrden_in ),
-// .rxoutclksel_in (rxoutclksel_in ),
-// .rxpcommaalignen_in (rxpcommaalignen_in ),
-// .rxpcsreset_in (rxpcsreset_in ),
-// .rxpd_in (rxpd_in ),
-// .rxphalign_in (rxphalign_in ),
-// .rxphalignen_in (rxphalignen_in ),
-// .rxphdlypd_in (rxphdlypd_in ),
-// .rxphdlyreset_in (rxphdlyreset_in ),
-// .rxpllclksel_in (rxpllclksel_in ),
-// .rxpmareset_in (rxpmareset_in ),
-// .rxpolarity_in (rxpolarity_in ),
-// .rxprbscntreset_in (rxprbscntreset_in ),
-// .rxprbssel_in (rxprbssel_in ),
-// .rxprogdivreset_in (rxprogdivreset_in ),
-// .rxrate_in (rxrate_in ),
-// .rxratemode_in (rxratemode_in ),
-// .rxslide_in (rxslide_in ),
-// .rxslipoutclk_in (rxslipoutclk_in ),
-// .rxslippma_in (rxslippma_in ),
-// .rxsyncallin_in (rxsyncallin_in ),
-// .rxsyncin_in (rxsyncin_in ),
-// .rxsyncmode_in (rxsyncmode_in ),
-// .rxsysclksel_in (rxsysclksel_in ),
-// .rxtermination_in (rxtermination_in ),
-// .rxuserrdy_in (rxuserrdy_in ),
-// .rxusrclk_in (rxusrclk_in ),
-// .rxusrclk2_in (rxusrclk2_in ),
-// .sigvalidclk_in (sigvalidclk_in ),
-// .tstin_in (tstin_in ),
-// .tx8b10bbypass_in (tx8b10bbypass_in ),
-// .tx8b10ben_in (tx8b10ben_in ),
-// .txcominit_in (txcominit_in ),
-// .txcomsas_in (txcomsas_in ),
-// .txcomwake_in (txcomwake_in ),
-// .txctrl0_in (txctrl0_in ),
-// .txctrl1_in (txctrl1_in ),
-// .txctrl2_in (txctrl2_in ),
-// .txdata_in (txdata_in ),
-// .txdataextendrsvd_in (txdataextendrsvd_in ),
-// .txdccforcestart_in (txdccforcestart_in ),
-// .txdccreset_in (txdccreset_in ),
-// .txdeemph_in (txdeemph_in ),
-// .txdetectrx_in (txdetectrx_in ),
-// .txdiffctrl_in (txdiffctrl_in ),
-// .txdlybypass_in (txdlybypass_in ),
-// .txdlyen_in (txdlyen_in ),
-// .txdlyhold_in (txdlyhold_in ),
-// .txdlyovrden_in (txdlyovrden_in ),
-// .txdlysreset_in (txdlysreset_in ),
-// .txdlyupdown_in (txdlyupdown_in ),
-// .txelecidle_in (txelecidle_in ),
-// .txheader_in (txheader_in ),
-// .txinhibit_in (txinhibit_in ),
-// .txlatclk_in (txlatclk_in ),
-// .txlfpstreset_in (txlfpstreset_in ),
-// .txlfpsu2lpexit_in (txlfpsu2lpexit_in ),
-// .txlfpsu3wake_in (txlfpsu3wake_in ),
-// .txmaincursor_in (txmaincursor_in ),
-// .txmargin_in (txmargin_in ),
-// .txmuxdcdexhold_in (txmuxdcdexhold_in ),
-// .txmuxdcdorwren_in (txmuxdcdorwren_in ),
-// .txoneszeros_in (txoneszeros_in ),
-// .txoutclksel_in (txoutclksel_in ),
-// .txpcsreset_in (txpcsreset_in ),
-// .txpd_in (txpd_in ),
-// .txpdelecidlemode_in (txpdelecidlemode_in ),
-// .txphalign_in (txphalign_in ),
-// .txphalignen_in (txphalignen_in ),
-// .txphdlypd_in (txphdlypd_in ),
-// .txphdlyreset_in (txphdlyreset_in ),
-// .txphdlytstclk_in (txphdlytstclk_in ),
-// .txphinit_in (txphinit_in ),
-// .txphovrden_in (txphovrden_in ),
-// .txpippmen_in (txpippmen_in ),
-// .txpippmovrden_in (txpippmovrden_in ),
-// .txpippmpd_in (txpippmpd_in ),
-// .txpippmsel_in (txpippmsel_in ),
-// .txpippmstepsize_in (txpippmstepsize_in ),
-// .txpisopd_in (txpisopd_in ),
-// .txpllclksel_in (txpllclksel_in ),
-// .txpmareset_in (txpmareset_in ),
-// .txpolarity_in (txpolarity_in ),
-// .txpostcursor_in (txpostcursor_in ),
-// .txprbsforceerr_in (txprbsforceerr_in ),
-// .txprbssel_in (txprbssel_in ),
-// .txprecursor_in (txprecursor_in ),
-// .txprogdivreset_in (txprogdivreset_in ),
-// .txrate_in (txrate_in ),
-// .txratemode_in (txratemode_in ),
-// .txsequence_in (txsequence_in ),
-// .txswing_in (txswing_in ),
-// .txsyncallin_in (txsyncallin_in ),
-// .txsyncin_in (txsyncin_in ),
-// .txsyncmode_in (txsyncmode_in ),
-// .txsysclksel_in (txsysclksel_in ),
-// .txuserrdy_in (txuserrdy_in ),
-// .txusrclk_in (txusrclk_in ),
-// .txusrclk2_in (txusrclk2_in ),
-// .bufgtce_out (bufgtce_out ),
-// .bufgtcemask_out (bufgtcemask_out ),
-// .bufgtdiv_out (bufgtdiv_out ),
-// .bufgtreset_out (bufgtreset_out ),
-// .bufgtrstmask_out (bufgtrstmask_out ),
-// .cpllfbclklost_out (cpllfbclklost_out ),
-// .cplllock_out (cplllock_out ),
-// .cpllrefclklost_out (cpllrefclklost_out ),
-// .dmonitorout_out (dmonitorout_out ),
-// .dmonitoroutclk_out (dmonitoroutclk_out ),
-// .drpdo_out (drpdo_out ),
-// .drprdy_out (drprdy_out ),
-// .eyescandataerror_out (eyescandataerror_out ),
-// .gtpowergood_out (gtpowergood_out ),
-// .gtrefclkmonitor_out (gtrefclkmonitor_out ),
-// .gtytxn_out (gtytxn_out ),
-// .gtytxp_out (gtytxp_out ),
-// .pcierategen3_out (pcierategen3_out ),
-// .pcierateidle_out (pcierateidle_out ),
-// .pcierateqpllpd_out (pcierateqpllpd_out ),
-// .pcierateqpllreset_out (pcierateqpllreset_out ),
-// .pciesynctxsyncdone_out (pciesynctxsyncdone_out ),
-// .pcieusergen3rdy_out (pcieusergen3rdy_out ),
-// .pcieuserphystatusrst_out (pcieuserphystatusrst_out ),
-// .pcieuserratestart_out (pcieuserratestart_out ),
-// .pcsrsvdout_out (pcsrsvdout_out ),
-// .phystatus_out (phystatus_out ),
-// .pinrsrvdas_out (pinrsrvdas_out ),
-// .powerpresent_out (powerpresent_out ),
-// .resetexception_out (resetexception_out ),
-// .rxbufstatus_out (rxbufstatus_out ),
-// .rxbyteisaligned_out (rxbyteisaligned_out ),
-// .rxbyterealign_out (rxbyterealign_out ),
-// .rxcdrlock_out (rxcdrlock_out ),
-// .rxcdrphdone_out (rxcdrphdone_out ),
-// .rxchanbondseq_out (rxchanbondseq_out ),
-// .rxchanisaligned_out (rxchanisaligned_out ),
-// .rxchanrealign_out (rxchanrealign_out ),
-// .rxchbondo_out (rxchbondo_out ),
-// .rxckcaldone_out (rxckcaldone_out ),
-// .rxclkcorcnt_out (rxclkcorcnt_out ),
-// .rxcominitdet_out (rxcominitdet_out ),
-// .rxcommadet_out (rxcommadet_out ),
-// .rxcomsasdet_out (rxcomsasdet_out ),
-// .rxcomwakedet_out (rxcomwakedet_out ),
-// .rxctrl0_out (rxctrl0_out ),
-// .rxctrl1_out (rxctrl1_out ),
-// .rxctrl2_out (rxctrl2_out ),
-// .rxctrl3_out (rxctrl3_out ),
-// .rxdata_out (rxdata_out ),
-// .rxdataextendrsvd_out (rxdataextendrsvd_out ),
-// .rxdatavalid_out (rxdatavalid_out ),
-// .rxdlysresetdone_out (rxdlysresetdone_out ),
-// .rxelecidle_out (rxelecidle_out ),
-// .rxheader_out (rxheader_out ),
-// .rxheadervalid_out (rxheadervalid_out ),
-// .rxlfpstresetdet_out (rxlfpstresetdet_out ),
-// .rxlfpsu2lpexitdet_out (rxlfpsu2lpexitdet_out ),
-// .rxlfpsu3wakedet_out (rxlfpsu3wakedet_out ),
-// .rxmonitorout_out (rxmonitorout_out ),
-// .rxosintdone_out (rxosintdone_out ),
-// .rxosintstarted_out (rxosintstarted_out ),
-// .rxosintstrobedone_out (rxosintstrobedone_out ),
-// .rxosintstrobestarted_out (rxosintstrobestarted_out ),
-// .rxoutclk_out (rxoutclk_out ),
-// .rxoutclkfabric_out (rxoutclkfabric_out ),
-// .rxoutclkpcs_out (rxoutclkpcs_out ),
-// .rxphaligndone_out (rxphaligndone_out ),
-// .rxphalignerr_out (rxphalignerr_out ),
-// .rxpmaresetdone_out (rxpmaresetdone_out ),
-// .rxprbserr_out (rxprbserr_out ),
-// .rxprbslocked_out (rxprbslocked_out ),
-// .rxprgdivresetdone_out (rxprgdivresetdone_out ),
-// .rxratedone_out (rxratedone_out ),
-// .rxrecclkout_out (rxrecclkout_out ),
-// .rxresetdone_out (rxresetdone_out ),
-// .rxsliderdy_out (rxsliderdy_out ),
-// .rxslipdone_out (rxslipdone_out ),
-// .rxslipoutclkrdy_out (rxslipoutclkrdy_out ),
-// .rxslippmardy_out (rxslippmardy_out ),
-// .rxstartofseq_out (rxstartofseq_out ),
-// .rxstatus_out (rxstatus_out ),
-// .rxsyncdone_out (rxsyncdone_out ),
-// .rxsyncout_out (rxsyncout_out ),
-// .rxvalid_out (rxvalid_out ),
-// .txbufstatus_out (txbufstatus_out ),
-// .txcomfinish_out (txcomfinish_out ),
-// .txdccdone_out (txdccdone_out ),
-// .txdlysresetdone_out (txdlysresetdone_out ),
-// .txoutclk_out (txoutclk_out ),
-// .txoutclkfabric_out (txoutclkfabric_out ),
-// .txoutclkpcs_out (txoutclkpcs_out ),
-// .txphaligndone_out (txphaligndone_out ),
-// .txphinitdone_out (txphinitdone_out ),
-// .txpmaresetdone_out (txpmaresetdone_out ),
-// .txprgdivresetdone_out (txprgdivresetdone_out ),
-// .txratedone_out (txratedone_out ),
-// .txresetdone_out (txresetdone_out ),
-// .txsyncdone_out (txsyncdone_out ),
-// .txsyncout_out (txsyncout_out )
-// );
-//
-// // Drive unused outputs to constant values
-// assign rxrecclk0_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign rxrecclk1_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
-// assign gthtxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign gthtxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign rxqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign txqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-// assign txqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
-
+ assign rxrecclk0_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign rxrecclk1_sel_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tcongpo_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign tconrsvdout0_out = {{`gtwizard_ultrascale_2_SF_CM}{1'b0}};
+ assign gthtxn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign gthtxp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign rxqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign txqpisenn_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+ assign txqpisenp_out = {{`gtwizard_ultrascale_2_N_CH}{1'b0}};
+*/
end
endgenerate
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v
old mode 100755
new mode 100644
index 75fccdc3dd47483f4678516a706dd829993a8639..a4e975129640838b22b4df938965352b9eb0fb32
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4/gtwizard_ultrascale_v1_7_gthe4_channel.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_7_7_gthe4_channel #(
+module gtwizard_ultrascale_v1_7_14_gthe4_channel #(
// -------------------------------------------------------------------------------------------------------------------