diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_7_gthe3_channel.v
old mode 100755
new mode 100644
similarity index 99%
rename from platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v
rename to platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_7_gthe3_channel.v
index eade4e5413b829212844876944e4f499e8df7538..d11ba9d5492eada7aa6aa0d984a680dc20e3f3bf
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_6_gthe3_channel.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/gtwizard_ultrascale_v1_7_gthe3_channel.v
@@ -52,7 +52,7 @@
`timescale 1ps/1ps
-module gtwizard_ultrascale_v1_6_5_gthe3_channel #(
+module gtwizard_ultrascale_v1_7_14_gthe3_channel #(
// -------------------------------------------------------------------------------------------------------------------
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v
index 1342a61c45ee2550dead2934400201a0d68fd61b..b89ab2db22dfe97064c4c81db0a9b03194660a47 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper.v
@@ -1,4 +1,4 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -47,17 +47,17 @@
// DO NOT MODIFY THIS FILE.
-// IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.6
-// IP Revision: 5
+// IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7
+// IP Revision: 14
-(* X_CORE_INFO = "wr_gth_wrapper_gtwizard_top,Vivado 2016.4" *)
+(* X_CORE_INFO = "wr_gth_wrapper_gtwizard_top,Vivado 2022.2" *)
(* CHECK_LICENSE_TYPE = "wr_gth_wrapper,wr_gth_wrapper_gtwizard_top,{}" *)
-(* CORE_GENERATION_INFO = "wr_gth_wrapper,wr_gth_wrapper_gtwizard_top,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.6,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=1,C_CPLL_VCO\
-_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=0,C_GT_REV=17,C_INCLUDE_CPLL_CAL=2,C_SIM_CPLL_CAL_BYPASS=0,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=2,C_LOCATE_RX_USER_CLOCKING=1,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=1,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP\
-=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_ENABLE=1,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=1,C_RX_COMMA\
-_P_VAL=0101111100,C_RX_DATA_DECODING=1,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=8,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_\
-SOURCE=0,C_RX_USER_DATA_WIDTH=16,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=1,C_TX_ENABLE=1,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX\
-=8,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=125.0000000,C_TX_OUTCLK_SOURCE=2,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=2,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=16,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
+(* CORE_GENERATION_INFO = "wr_gth_wrapper,wr_gth_wrapper_gtwizard_top,{x_ipProduct=Vivado 2022.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.7,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=1,C_CPLL_VCO_F\
+REQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=0,C_GT_REV=17,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=0,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=2,C_LOCATE_RX_USER_CLOCKING=1,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=1,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0,C_RX_BUFFER_B\
+YPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_ENABLE=1,C_RX_CO\
+MMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=1,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=1,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=8,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_RX_USER_\
+CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=16,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=1,C_TX_ENABLE=1,C_TX_INT_DATA\
+_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=8,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=125.0000000,C_TX_OUTCLK_SOURCE=2,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=2,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=16,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module wr_gth_wrapper (
gtwiz_userclk_tx_active_in,
@@ -100,6 +100,7 @@ module wr_gth_wrapper (
txusrclk2_in,
gthtxn_out,
gthtxp_out,
+ gtpowergood_out,
rxbyteisaligned_out,
rxbyterealign_out,
rxcommadet_out,
@@ -153,6 +154,7 @@ input wire [0 : 0] txusrclk_in;
input wire [0 : 0] txusrclk2_in;
output wire [0 : 0] gthtxn_out;
output wire [0 : 0] gthtxp_out;
+output wire [0 : 0] gtpowergood_out;
output wire [0 : 0] rxbyteisaligned_out;
output wire [0 : 0] rxbyterealign_out;
output wire [0 : 0] rxcommadet_out;
@@ -176,7 +178,9 @@ output wire [0 : 0] txpmaresetdone_out;
.C_GT_TYPE(0),
.C_GT_REV(17),
.C_INCLUDE_CPLL_CAL(2),
- .C_SIM_CPLL_CAL_BYPASS(1'B0),
+ .C_ENABLE_COMMON_USRCLK(0),
+ .C_USER_GTPOWERGOOD_DELAY_EN(0),
+ .C_SIM_CPLL_CAL_BYPASS(1),
.C_LOCATE_COMMON(0),
.C_LOCATE_RESET_CONTROLLER(0),
.C_LOCATE_USER_DATA_WIDTH_SIZING(0),
@@ -700,7 +704,7 @@ output wire [0 : 0] txpmaresetdone_out;
.eyescandataerror_out(),
.gthtxn_out(gthtxn_out),
.gthtxp_out(gthtxp_out),
- .gtpowergood_out(),
+ .gtpowergood_out(gtpowergood_out),
.gtrefclkmonitor_out(),
.gtytxn_out(),
.gtytxp_out(),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v
index de982528c118000f9c802c64e74b94cc716b795e..dc6060db1319df58fffff71a049392477a39454f 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_bit_sync.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v
index e5607a8cdf263ecac90d680cd008ae04cb24bbe9..abb58017a167aef9079bb84ba07852ca89581460 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_rx.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v
index 7212ea9e90964b7e83cc69a2b4519dc759f91e04..10d5ce53fcd0c99ea81c865f192a940885e4fc92 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_gtwiz_userclk_tx.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_init.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_init.v
index 00387170ec54f5dc27ecf492ff7b0b93b51d0c54..3f159e8cabe56f1ce8a6bc68ca39bee4152731eb 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_init.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_init.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -59,8 +59,8 @@
module wr_gth_wrapper_example_init # (
parameter real P_FREERUN_FREQUENCY = 62.5,
- parameter real P_TX_TIMER_DURATION_US = 300,
- parameter real P_RX_TIMER_DURATION_US = 300
+ parameter real P_TX_TIMER_DURATION_US = 30000,
+ parameter real P_RX_TIMER_DURATION_US = 130000
)(
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v
index 4d4eacda57ac37443bcc93c8d7d8de0a4fa1ca73..3189ca666a87af0a73d186c3bb3eb3f7f9eb1953 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_reset_sync.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_top.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_top.v
index 9ba1d1c1380d7bfd6d34f68e347e070111bb9dac..8a232198c3c4d4ae95cd351d2dec690a989cd005 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_top.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_top.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -77,12 +77,12 @@ module wr_gth_wrapper_example_top (
input rx_slide_i,
output rx_byte_is_aligned_o,
output rx_comma_det_o,
-
+
output rx_clk_o,
input [1:0] tx_k_i,
output [1:0] rx_k_o,
-
- output ready_o
+
+ output ready_o
);
@@ -213,12 +213,12 @@ module wr_gth_wrapper_example_top (
assign gtwiz_reset_all_int[0:0] = hb0_gtwiz_reset_all_int;
//--------------------------------------------------------------------------------------------------------------------
- wire [0:0] gtwiz_reset_tx_pll_and_datapath_int = 1'b0;
+ wire [0:0] gtwiz_reset_tx_pll_and_datapath_int;
wire [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int;
assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int;
//--------------------------------------------------------------------------------------------------------------------
- wire [0:0] gtwiz_reset_tx_datapath_int = 1'b0;
+ wire [0:0] gtwiz_reset_tx_datapath_int;
wire [0:0] hb0_gtwiz_reset_tx_datapath_int;
assign gtwiz_reset_tx_datapath_int[0:0] = hb0_gtwiz_reset_tx_datapath_int;
@@ -279,12 +279,12 @@ module wr_gth_wrapper_example_top (
//--------------------------------------------------------------------------------------------------------------------
wire [0:0] rxmcommaalignen_int;
- wire [0:0] ch0_rxmcommaalignen_int = 1'b0;
+ wire [0:0] ch0_rxmcommaalignen_int = 1'b1;
assign rxmcommaalignen_int[0:0] = ch0_rxmcommaalignen_int;
//--------------------------------------------------------------------------------------------------------------------
wire [0:0] rxpcommaalignen_int;
- wire [0:0] ch0_rxpcommaalignen_int = 1'b0;
+ wire [0:0] ch0_rxpcommaalignen_int = 1'b1;
assign rxpcommaalignen_int[0:0] = ch0_rxpcommaalignen_int;
@@ -294,6 +294,12 @@ module wr_gth_wrapper_example_top (
wire [0:0] ch0_tx8b10ben_int = 1'b1;
assign tx8b10ben_int[0:0] = ch0_tx8b10ben_int;
+
+ //--------------------------------------------------------------------------------------------------------------------
+ wire [0:0] gtpowergood_int;
+ wire [0:0] ch0_gtpowergood_int;
+ assign ch0_gtpowergood_int = gtpowergood_int[0:0];
+
//--------------------------------------------------------------------------------------------------------------------
wire [0:0] rxbyteisaligned_int;
wire [0:0] ch0_rxbyteisaligned_int;
@@ -351,11 +357,11 @@ module wr_gth_wrapper_example_top (
wire hb_gtwiz_reset_all_init_int;
wire hb_gtwiz_reset_all_int;
- assign hb_gtwiz_reset_all_buf_int = hb_gtwiz_reset_all_in;
-
+ assign hb_gtwiz_reset_all_buf_int = hb_gtwiz_reset_all_in;
+
+
+ assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int;
- assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int;
-
// Globally buffer the free-running input clock
wire hb_gtwiz_reset_clk_freerun_buf_int;
@@ -429,10 +435,10 @@ module wr_gth_wrapper_example_top (
assign tx_clk_o = hb0_gtwiz_userclk_tx_usrclk2_int;
assign rx_clk_o = hb0_gtwiz_userclk_rx_usrclk2_int;
-
+
assign hb0_gtwiz_userdata_tx_int = tx_data_i;
assign rx_data_o = hb0_gtwiz_userdata_rx_int;
-
+
assign ready_o = ~(hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int || ~hb0_gtwiz_buffbypass_tx_done_int);
@@ -446,7 +452,7 @@ module wr_gth_wrapper_example_top (
assign txctrl2_int = {6'b0, tx_k_i};
assign rx_k_o = rxctrl0_int[1:0];
-
+
// ===================================================================================================================
// INITIALIZATION
// ===================================================================================================================
@@ -464,7 +470,8 @@ module wr_gth_wrapper_example_top (
// controller helper block reset input
wire hb_gtwiz_reset_rx_datapath_init_int;
- assign hb_gtwiz_reset_rx_datapath_int = hb_gtwiz_reset_rx_datapath_init_int ;
+ assign hb_gtwiz_reset_rx_datapath_int = hb_gtwiz_reset_rx_datapath_init_int;
+
// The example initialization module interacts with the reset controller helper block and other example design logic
// to retry failed reset attempts in order to mitigate bring-up issues such as initially-unavilable reference clocks
@@ -535,6 +542,7 @@ module wr_gth_wrapper_example_top (
,.txctrl0_in (txctrl0_int)
,.txctrl1_in (txctrl1_int)
,.txctrl2_in (txctrl2_int)
+ ,.gtpowergood_out (gtpowergood_int)
,.rxbyteisaligned_out (rx_byte_is_aligned_o)
,.rxbyterealign_out (rxbyterealign_int)
,.rxcommadet_out (rx_comma_det_o)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v
index 2326c04c0ef0156b5080af10d04536f7c18c25d2..437db14bb4bb192c3e2e877c333cf375bfbb289d 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -99,6 +99,7 @@ module wr_gth_wrapper_example_wrapper (
,input wire [15:0] txctrl0_in
,input wire [15:0] txctrl1_in
,input wire [7:0] txctrl2_in
+ ,output wire [0:0] gtpowergood_out
,output wire [0:0] rxbyteisaligned_out
,output wire [0:0] rxbyterealign_out
,output wire [0:0] rxcommadet_out
@@ -117,8 +118,6 @@ module wr_gth_wrapper_example_wrapper (
// Declare and initialize local parameters and functions used for HDL generation
localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000;
-
-`define INCLUDE_WRAPPER_FUNCTIONS 1
`include "wr_gth_wrapper_example_wrapper_functions.v"
localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8);
localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8);
@@ -184,6 +183,10 @@ module wr_gth_wrapper_example_wrapper (
// Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs
assign rxusrclk_int = {1{gtwiz_userclk_rx_usrclk_out}};
assign rxusrclk2_int = {1{gtwiz_userclk_rx_usrclk2_out}};
+ wire [0:0] gtpowergood_int;
+
+ // Required assignment to expose the GTPOWERGOOD port per user request
+ assign gtpowergood_out = gtpowergood_int;
// ----------------------------------------------------------------------------------------------------------------
// Assignments to expose data ports, or data control ports, per configuration requirement or user request
@@ -253,6 +256,7 @@ module wr_gth_wrapper_example_wrapper (
,.txctrl2_in (txctrl2_in)
,.txusrclk_in (txusrclk_int)
,.txusrclk2_in (txusrclk2_int)
+ ,.gtpowergood_out (gtpowergood_int)
,.rxbyteisaligned_out (rxbyteisaligned_out)
,.rxbyterealign_out (rxbyterealign_out)
,.rxcommadet_out (rxcommadet_out)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v
index 81d4ef39fb4914d691035d1dccaf0c143d5e7291..b158f07725771a6c5048f443da84461d21110f0f 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_example_wrapper_functions.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -46,7 +46,7 @@
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
-`ifdef INCLUDE_WRAPPER_FUNCTIONS
+
// =====================================================================================================================
// This file contains functions available for example design HDL generation as required
// =====================================================================================================================
@@ -239,5 +239,3 @@ begin : main_f_idx_ch_lb
f_idx_ch_lb = result - 1;
end
endfunction
-
-`endif
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v
index 45adc39cbdfdabbda1a55be291219b992500c580..7545a371714035d3815266461cf59ce76a03e2d1 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gthe3_channel_wrapper.v
@@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
-// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
@@ -391,7 +391,7 @@ module wr_gth_wrapper_gthe3_channel_wrapper #(
-gtwizard_ultrascale_v1_6_5_gthe3_channel #(
+gtwizard_ultrascale_v1_7_14_gthe3_channel #(
.GTHE3_CHANNEL_ACJTAG_DEBUG_MODE (1'b0),
.GTHE3_CHANNEL_ACJTAG_MODE (1'b0),
.GTHE3_CHANNEL_ACJTAG_RESET (1'b0),
@@ -1145,7 +1145,7 @@ gtwizard_ultrascale_v1_6_5_gthe3_channel #(
.GTHE3_CHANNEL_TXPI_CFG4 (1'b1),
.GTHE3_CHANNEL_TXPI_CFG5 (3'b011),
.GTHE3_CHANNEL_TXPI_GRAY_SEL (1'b0),
- .GTHE3_CHANNEL_TXPI_INVSTROBE_SEL (1'b0),
+ .GTHE3_CHANNEL_TXPI_INVSTROBE_SEL (1'b1),
.GTHE3_CHANNEL_TXPI_LPM (1'b0),
.GTHE3_CHANNEL_TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.GTHE3_CHANNEL_TXPI_PPM_CFG (8'b00000000),
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v
index e39363d8cc0ebad79851e4465dee106f8e18f355..b8e466d15c251f605d848c7ef26bd94252af68ee 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_gthe3.v
@@ -57,9 +57,13 @@
`define wr_gth_wrapper_gtwizard_gthe3_N_CM C_TOTAL_NUM_COMMONS
`define wr_gth_wrapper_gtwizard_gthe3_N_CH C_TOTAL_NUM_CHANNELS
`define wr_gth_wrapper_gtwizard_gthe3_SF_CM C_COMMON_SCALING_FACTOR
+`define wr_gth_wrapper_gtwizard_gthe3_DEFAULT_CLOCKING 0
+`define wr_gth_wrapper_gtwizard_gthe3_TX_USES_RX_CLOCKING 1
+`define wr_gth_wrapper_gtwizard_gthe3_RX_USES_TX_CLOCKING 2
`define wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__EXCLUDE 0
`define wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__INCLUDE 1
`define wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__DEPENDENT 2
+`define wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__PCIEQMODE 3
`define wr_gth_wrapper_gtwizard_gthe3_LOCATE_RESET_CONTROLLER__CORE 0
`define wr_gth_wrapper_gtwizard_gthe3_LOCATE_RESET_CONTROLLER__EXAMPLE_DESIGN 1
`define wr_gth_wrapper_gtwizard_gthe3_LOCATE_USER_DATA_WIDTH_SIZING__CORE 0
@@ -134,6 +138,7 @@
`define wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_INSTANCE_CTRL__PER_CHANNEL 1
`define wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__TXOUTCLK 0
`define wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__IBUFDS 1
+`define wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__RXOUTCLK 2
module wr_gth_wrapper_gtwizard_gthe3 #(
@@ -145,6 +150,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
parameter real C_FREERUN_FREQUENCY = 200,
parameter integer C_GT_REV = 17,
parameter integer C_INCLUDE_CPLL_CAL = `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__DEPENDENT,
+ parameter integer C_ENABLE_COMMON_USRCLK = `wr_gth_wrapper_gtwizard_gthe3_DEFAULT_CLOCKING,
parameter integer C_LOCATE_RESET_CONTROLLER = `wr_gth_wrapper_gtwizard_gthe3_LOCATE_RESET_CONTROLLER__CORE,
parameter integer C_LOCATE_USER_DATA_WIDTH_SIZING = `wr_gth_wrapper_gtwizard_gthe3_LOCATE_USER_DATA_WIDTH_SIZING__CORE,
parameter integer C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = `wr_gth_wrapper_gtwizard_gthe3_LOCATE_RX_BUFFER_BYPASS_CONTROLLER__CORE,
@@ -2182,6 +2188,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// If the transceiver channel CPLL calibration block is required, instantiate it for each transceiver channel
if ((C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__INCLUDE) ||
+ (C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__PCIEQMODE) ||
(((C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__DEPENDENT) &&
((C_GT_REV == 11) ||
(C_GT_REV == 12) ||
@@ -2218,12 +2225,14 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
wire [ `wr_gth_wrapper_gtwizard_gthe3_N_CH -1:0] drpen_cpll_cal_int;
wire [ `wr_gth_wrapper_gtwizard_gthe3_N_CH -1:0] drpwe_cpll_cal_int;
- // The TXOUTCLK_PERIOD_IN and CNT_TOL_IN ports are normally driven by an internally-calculated value. When INCLUDE_CPLL_CAL is 1,
+ // The TXOUTCLK_PERIOD_IN and CNT_TOL_IN ports are normally driven by an internally-calculated value. When INCLUDE_CPLL_CAL is 1/3,
// they are driven as inputs for PLL-switching and rate change special cases, and the BUFG_GT CE input is provided by the user.
wire [(`wr_gth_wrapper_gtwizard_gthe3_N_CH* 18)-1:0] cpll_cal_txoutclk_period_int;
wire [(`wr_gth_wrapper_gtwizard_gthe3_N_CH* 18)-1:0] cpll_cal_cnt_tol_int;
wire [(`wr_gth_wrapper_gtwizard_gthe3_N_CH* 1)-1:0] cpll_cal_bufg_ce_int;
- if (C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__INCLUDE) begin : gen_txoutclk_pd_input
+ if ((C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__INCLUDE) ||
+ (C_INCLUDE_CPLL_CAL == `wr_gth_wrapper_gtwizard_gthe3_INCLUDE_CPLL_CAL__PCIEQMODE)
+ ) begin : gen_txoutclk_pd_input
assign cpll_cal_txoutclk_period_int = {`wr_gth_wrapper_gtwizard_gthe3_N_CH{gtwiz_gthe3_cpll_cal_txoutclk_period_in}};
assign cpll_cal_cnt_tol_int = {`wr_gth_wrapper_gtwizard_gthe3_N_CH{gtwiz_gthe3_cpll_cal_cnt_tol_in}};
assign cpll_cal_bufg_ce_int = {`wr_gth_wrapper_gtwizard_gthe3_N_CH{gtwiz_gthe3_cpll_cal_bufg_ce_in}};
@@ -2241,7 +2250,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// Instantiate one CPLL calibration block for each transceiver channel
genvar cal;
for (cal = 0; cal < `wr_gth_wrapper_gtwizard_gthe3_N_CH; cal = cal + 1) begin : gen_cpll_cal_inst
- gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal gtwizard_ultrascale_v1_7_7_gthe3_cpll_cal_inst (
+ gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal gtwizard_ultrascale_v1_7_14_gthe3_cpll_cal_inst (
.TXOUTCLK_PERIOD_IN (cpll_cal_txoutclk_period_int[(18*cal)+17:18*cal]),
.WAIT_DEASSERT_CPLLPD_IN (p_cpll_cal_wait_deassert_cpllpd_int),
.CNT_TOL_IN (cpll_cal_cnt_tol_int[(18*cal)+17:18*cal]),
@@ -2313,9 +2322,8 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// within this inactive generate block for proper HDL fileset hierarchy elaboration
if (0) begin : gen_cpll_cal_gthe4
- gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal gtwizard_ultrascale_v1_7_7_gthe4_cpll_cal_inst (
+ gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal gtwizard_ultrascale_v1_7_14_gthe4_cpll_cal_inst (
.TXOUTCLK_PERIOD_IN (18'b0),
- .WAIT_DEASSERT_CPLLPD_IN (16'b0),
.CNT_TOL_IN (18'b0),
.FREQ_COUNT_WINDOW_IN (16'b0),
.RESET_IN (1'b0),
@@ -2355,9 +2363,8 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
end
if (0) begin : gen_cpll_cal_gtye4
- gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal gtwizard_ultrascale_v1_7_7_gtye4_cpll_cal_inst (
+ gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal gtwizard_ultrascale_v1_7_14_gtye4_cpll_cal_inst (
.TXOUTCLK_PERIOD_IN (18'b0),
- .WAIT_DEASSERT_CPLLPD_IN (16'b0),
.CNT_TOL_IN (18'b0),
.FREQ_COUNT_WINDOW_IN (16'b0),
.RESET_IN (1'b0),
@@ -2424,6 +2431,8 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// ================================================================================================================
// HELPER BLOCKS
// ================================================================================================================
+ wire [(C_TX_USER_CLOCKING_INSTANCE_CTRL*(`wr_gth_wrapper_gtwizard_gthe3_N_CH-1)):0] gtwiz_userclk_tx_reset_int;
+ wire [(C_RX_USER_CLOCKING_INSTANCE_CTRL*(`wr_gth_wrapper_gtwizard_gthe3_N_CH-1)):0] gtwiz_userclk_rx_reset_int;
// ----------------------------------------------------------------------------------------------------------------
// Transmitter user clocking network helper block
@@ -2441,6 +2450,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// The source clock is TXOUTCLK from the master transmitter channel
if (C_TX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__TXOUTCLK) begin : gen_txoutclk_source
assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX];
+ assign gtwiz_userclk_tx_reset_int = gtwiz_userclk_tx_reset_in;
end
// The source clock is the fabric-accessible output of the IBUFDS_GTE3 associated with the master transmitter
@@ -2455,16 +2465,21 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
else begin: gen_ibufds_source_cpll
assign gtwiz_userclk_tx_srcclk_out = gtrefclk0_int[P_TX_MASTER_CH_PACKED_IDX];
end
+ assign gtwiz_userclk_tx_reset_int = gtwiz_userclk_tx_reset_in;
+ end
+ else if (C_TX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__RXOUTCLK) begin : gen_rxoutclk_source
+ assign gtwiz_userclk_tx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX];
+ assign gtwiz_userclk_tx_reset_int = gtwiz_userclk_rx_reset_in;
end
// Instantiate a single instance of the transmitter user clocking network helper block
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
.P_CONTENTS (C_TX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_TX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
) gtwiz_userclk_tx_inst (
.gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out),
- .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in),
+ .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int),
.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out),
.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out),
.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out)
@@ -2488,6 +2503,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// The source clock for a given instance is TXOUTCLK from the associated channel
if (C_TX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__TXOUTCLK) begin : gen_txoutclk_source
assign gtwiz_userclk_tx_srcclk_out[gi_hb_txclk] = txoutclk_int[gi_hb_txclk];
+ assign gtwiz_userclk_tx_reset_int[gi_hb_txclk] = gtwiz_userclk_tx_reset_in[gi_hb_txclk];
end
// The source clock for a given instance is the fabric-accessible output of the IBUFDS_GTE3 associated with that
@@ -2502,15 +2518,20 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
else begin: gen_ibufds_source_cpll
assign gtwiz_userclk_tx_srcclk_out[gi_hb_txclk] = gtrefclk0_int[gi_hb_txclk];
end
+ assign gtwiz_userclk_tx_reset_int[gi_hb_txclk] = gtwiz_userclk_tx_reset_in[gi_hb_txclk];
+ end
+ else if (C_TX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_SOURCE__RXOUTCLK) begin : gen_rxoutclk_source
+ assign gtwiz_userclk_tx_srcclk_out[gi_hb_txclk] = rxoutclk_int[gi_hb_txclk];
+ assign gtwiz_userclk_tx_reset_int[gi_hb_txclk] = gtwiz_userclk_rx_reset_in[gi_hb_txclk];
end
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_tx #(
.P_CONTENTS (C_TX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_TX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
) gtwiz_userclk_tx_inst (
.gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out [gi_hb_txclk]),
- .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in [gi_hb_txclk]),
+ .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int [gi_hb_txclk]),
.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out [gi_hb_txclk]),
.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out [gi_hb_txclk]),
.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out [gi_hb_txclk])
@@ -2528,6 +2549,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// Do not include the helper block within the core
else begin : gen_tx_user_clocking_external
+ assign gtwiz_userclk_tx_reset_int = gtwiz_userclk_tx_reset_in;
if (C_TX_USER_CLOCKING_INSTANCE_CTRL == `wr_gth_wrapper_gtwizard_gthe3_TX_USER_CLOCKING_INSTANCE_CTRL__SINGLE_INSTANCE)
begin : gen_single_instance
assign gtwiz_userclk_tx_srcclk_out = 1'b0;
@@ -2562,6 +2584,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// The source clock is RXOUTCLK from the master receiver channel
if (C_RX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_RX_USER_CLOCKING_SOURCE__RXOUTCLK) begin : gen_rxoutclk_source
assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX];
+ assign gtwiz_userclk_rx_reset_int = gtwiz_userclk_rx_reset_in;
end
// The source clock is the fabric-accessible output of the IBUFDS_GTE3 associated with the master receiver
@@ -2576,21 +2599,23 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
else begin: gen_ibufds_source_cpll
assign gtwiz_userclk_rx_srcclk_out = gtrefclk0_int[P_RX_MASTER_CH_PACKED_IDX];
end
+ assign gtwiz_userclk_rx_reset_int = gtwiz_userclk_rx_reset_in;
end
// The source clock is TXOUTCLK from the master transmitter channel
else if (C_RX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_RX_USER_CLOCKING_SOURCE__TXOUTCLK) begin : gen_txoutclk_source
assign gtwiz_userclk_rx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX];
+ assign gtwiz_userclk_rx_reset_int = gtwiz_userclk_tx_reset_in;
end
// Instantiate a single instance of the receiver user clocking network helper block
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
.P_CONTENTS (C_RX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_RX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
) gtwiz_userclk_rx_inst (
.gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out),
- .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in),
+ .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int),
.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out),
.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out),
.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out)
@@ -2614,6 +2639,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// The source clock for a given instance is RXOUTCLK from the associated channel
if (C_RX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_RX_USER_CLOCKING_SOURCE__RXOUTCLK) begin : gen_rxoutclk_source
assign gtwiz_userclk_rx_srcclk_out[gi_hb_rxclk] = rxoutclk_int[gi_hb_rxclk];
+ assign gtwiz_userclk_rx_reset_int[gi_hb_rxclk] = gtwiz_userclk_rx_reset_in[gi_hb_rxclk];
end
// The source clock for a given instance is the fabric-accessible output of the IBUFDS_GTE3 associated with that
@@ -2628,20 +2654,22 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
else begin: gen_ibufds_source_cpll
assign gtwiz_userclk_rx_srcclk_out[gi_hb_rxclk] = gtrefclk0_int[gi_hb_rxclk];
end
+ assign gtwiz_userclk_rx_reset_int[gi_hb_rxclk] = gtwiz_userclk_rx_reset_in[gi_hb_rxclk];
end
// The source clock for a given instance is TXOUTCLK from the associated channel
else if (C_RX_USER_CLOCKING_SOURCE == `wr_gth_wrapper_gtwizard_gthe3_RX_USER_CLOCKING_SOURCE__TXOUTCLK) begin : gen_txoutclk_source
assign gtwiz_userclk_rx_srcclk_out[gi_hb_rxclk] = txoutclk_int[gi_hb_rxclk];
+ assign gtwiz_userclk_rx_reset_int[gi_hb_rxclk] = gtwiz_userclk_tx_reset_in;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_userclk_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userclk_rx #(
.P_CONTENTS (C_RX_USER_CLOCKING_CONTENTS),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (C_RX_OUTCLK_BUFG_GT_DIV),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2)
) gtwiz_userclk_rx_inst (
.gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out [gi_hb_rxclk]),
- .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in [gi_hb_rxclk]),
+ .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int [gi_hb_rxclk]),
.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out [gi_hb_rxclk]),
.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out [gi_hb_rxclk]),
.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out [gi_hb_rxclk])
@@ -2659,6 +2687,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
// Do not include the helper block within the core
else begin : gen_rx_user_clocking_external
+ assign gtwiz_userclk_rx_reset_int = gtwiz_userclk_rx_reset_in;
if (C_RX_USER_CLOCKING_INSTANCE_CTRL == `wr_gth_wrapper_gtwizard_gthe3_RX_USER_CLOCKING_INSTANCE_CTRL__SINGLE_INSTANCE)
begin : gen_single_instance
assign gtwiz_userclk_rx_srcclk_out = 1'b0;
@@ -2704,7 +2733,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
assign gtwiz_buffbypass_tx_resetdone_int = >wiz_reset_tx_done_out;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
.P_BUFFER_BYPASS_MODE (C_TX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS),
.P_MASTER_CHANNEL_POINTER (P_TX_MASTER_CH_PACKED_IDX)
@@ -2759,7 +2788,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
genvar gi_hb_txbb;
for (gi_hb_txbb = 0; gi_hb_txbb < `wr_gth_wrapper_gtwizard_gthe3_N_CH; gi_hb_txbb = gi_hb_txbb + 1) begin : gen_gtwiz_buffbypass_tx
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_tx #(
.P_BUFFER_BYPASS_MODE (C_TX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (1),
.P_MASTER_CHANNEL_POINTER (0)
@@ -2858,7 +2887,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
assign gtwiz_buffbypass_rx_resetdone_int = >wiz_reset_rx_done_out;
end
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
.P_BUFFER_BYPASS_MODE (C_RX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS),
.P_MASTER_CHANNEL_POINTER (P_RX_MASTER_CH_PACKED_IDX)
@@ -2908,7 +2937,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
genvar gi_hb_rxbb;
for (gi_hb_rxbb = 0; gi_hb_rxbb < `wr_gth_wrapper_gtwizard_gthe3_N_CH; gi_hb_rxbb = gi_hb_rxbb + 1) begin : gen_gtwiz_buffbypass_rx
- gtwizard_ultrascale_v1_7_7_gtwiz_buffbypass_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_buffbypass_rx #(
.P_BUFFER_BYPASS_MODE (C_RX_BUFFBYPASS_MODE),
.P_TOTAL_NUMBER_OF_CHANNELS (1),
.P_MASTER_CHANNEL_POINTER (0)
@@ -3007,7 +3036,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
genvar gi_ch_rxclk;
for (gi_ch_rxclk = 0; gi_ch_rxclk < `wr_gth_wrapper_gtwizard_gthe3_N_CH; gi_ch_rxclk = gi_ch_rxclk + 1) begin : gen_ch_rxclk
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (gtwiz_userclk_rx_active_out[gi_ch_rxclk]),
.o_out (gtwiz_userclk_rx_active_sync[gi_ch_rxclk])
@@ -3052,12 +3081,12 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
wire [`wr_gth_wrapper_gtwizard_gthe3_N_CH-1:0] rxresetdone_sync;
genvar gi_ch_xrd;
for (gi_ch_xrd = 0; gi_ch_xrd < `wr_gth_wrapper_gtwizard_gthe3_N_CH; gi_ch_xrd = gi_ch_xrd + 1) begin : gen_ch_xrd
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_txresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_txresetdone_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (txresetdone_int[gi_ch_xrd]),
.o_out (txresetdone_sync[gi_ch_xrd])
);
- gtwizard_ultrascale_v1_7_7_bit_synchronizer bit_synchronizer_rxresetdone_inst (
+ gtwizard_ultrascale_v1_7_14_bit_synchronizer bit_synchronizer_rxresetdone_inst (
.clk_in (gtwiz_reset_clk_freerun_in),
.i_in (rxresetdone_int[gi_ch_xrd]),
.o_out (rxresetdone_sync[gi_ch_xrd])
@@ -3096,7 +3125,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
end
// Instantiate the single reset controller
- gtwizard_ultrascale_v1_7_7_gtwiz_reset #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_reset #(
.P_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY),
.P_USE_CPLL_CAL (P_USE_CPLL_CAL),
.P_TX_PLL_TYPE (C_TX_PLL_TYPE),
@@ -3348,7 +3377,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
endcase
// Instantiate a reset controller per channel
- gtwizard_ultrascale_v1_7_7_gtwiz_reset #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_reset #(
.P_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY),
.P_USE_CPLL_CAL (P_USE_CPLL_CAL),
.P_TX_PLL_TYPE (C_TX_PLL_TYPE),
@@ -3549,7 +3578,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
wire [(C_TOTAL_NUM_CHANNELS* 16)-1:0] gtwiz_userdata_tx_txctrl0_int;
wire [(C_TOTAL_NUM_CHANNELS* 16)-1:0] gtwiz_userdata_tx_txctrl1_int;
- gtwizard_ultrascale_v1_7_7_gtwiz_userdata_tx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userdata_tx #(
.P_TX_USER_DATA_WIDTH (C_TX_USER_DATA_WIDTH),
.P_TX_DATA_ENCODING (C_TX_DATA_ENCODING),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS)
@@ -3595,7 +3624,7 @@ module wr_gth_wrapper_gtwizard_gthe3 #(
(C_LOCATE_USER_DATA_WIDTH_SIZING == `wr_gth_wrapper_gtwizard_gthe3_LOCATE_USER_DATA_WIDTH_SIZING__CORE))
begin : gen_rx_userdata_internal
- gtwizard_ultrascale_v1_7_7_gtwiz_userdata_rx #(
+ gtwizard_ultrascale_v1_7_14_gtwiz_userdata_rx #(
.P_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH),
.P_RX_DATA_DECODING (C_RX_DATA_DECODING),
.P_TOTAL_NUMBER_OF_CHANNELS (C_TOTAL_NUM_CHANNELS)
diff --git a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v
index a76147b53ecc8181d03ed2b68980ea37d64c286b..8c797a61cc65a4d146f8acbdd3e86deae64aa5a5 100644
--- a/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v
+++ b/platform/xilinx/wr_gtp_phy/xilinx-ip/gthe3/wr_gth_wrapper_gtwizard_top.v
@@ -63,9 +63,13 @@
`define wr_gth_wrapper_GT_TYPE__GTYE3 1
`define wr_gth_wrapper_GT_TYPE__GTHE4 2
`define wr_gth_wrapper_GT_TYPE__GTYE4 3
+`define wr_gth_wrapper_DEFAULT_CLOCKING 0
+`define wr_gth_wrapper_TX_USES_RX_CLOCKING 1
+`define wr_gth_wrapper_RX_USES_TX_CLOCKING 2
`define wr_gth_wrapper_INCLUDE_CPLL_CAL__EXCLUDE 0
`define wr_gth_wrapper_INCLUDE_CPLL_CAL__INCLUDE 1
`define wr_gth_wrapper_INCLUDE_CPLL_CAL__DEPENDENT 2
+`define wr_gth_wrapper_INCLUDE_CPLL_CAL__PCIEQMODE 3
`define wr_gth_wrapper_LOCATE_COMMON__CORE 0
`define wr_gth_wrapper_LOCATE_COMMON__EXAMPLE_DESIGN 1
`define wr_gth_wrapper_LOCATE_RESET_CONTROLLER__CORE 0
@@ -166,6 +170,7 @@
`define wr_gth_wrapper_TX_USER_CLOCKING_INSTANCE_CTRL__PER_CHANNEL 1
`define wr_gth_wrapper_TX_USER_CLOCKING_SOURCE__TXOUTCLK 0
`define wr_gth_wrapper_TX_USER_CLOCKING_SOURCE__IBUFDS 1
+`define wr_gth_wrapper_TX_USER_CLOCKING_SOURCE__RXOUTCLK 2
module wr_gth_wrapper_gtwizard_top #(
@@ -179,7 +184,9 @@ module wr_gth_wrapper_gtwizard_top #(
parameter integer C_GT_TYPE = `wr_gth_wrapper_GT_TYPE__GTHE3,
parameter integer C_GT_REV = 17,
parameter integer C_INCLUDE_CPLL_CAL = `wr_gth_wrapper_INCLUDE_CPLL_CAL__DEPENDENT,
- parameter C_SIM_CPLL_CAL_BYPASS = 1'b0,
+ parameter integer C_ENABLE_COMMON_USRCLK = `wr_gth_wrapper_DEFAULT_CLOCKING,
+ parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
+ parameter C_SIM_CPLL_CAL_BYPASS = 1,
parameter integer C_LOCATE_COMMON = `wr_gth_wrapper_LOCATE_COMMON__CORE,
parameter integer C_LOCATE_RESET_CONTROLLER = `wr_gth_wrapper_LOCATE_RESET_CONTROLLER__CORE,
parameter integer C_LOCATE_USER_DATA_WIDTH_SIZING = `wr_gth_wrapper_LOCATE_USER_DATA_WIDTH_SIZING__CORE,
@@ -1277,6 +1284,7 @@ module wr_gth_wrapper_gtwizard_top #(
.C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
.C_GT_REV (C_GT_REV ),
.C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
.C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
.C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
.C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
@@ -1791,6 +1799,7 @@ module wr_gth_wrapper_gtwizard_top #(
.C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
.C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
.C_GT_REV (C_GT_REV ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
.C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
.C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
.C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER (C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER ),
@@ -2306,8 +2315,12 @@ module wr_gth_wrapper_gtwizard_top #(
.C_PCIE_ENABLE (C_PCIE_ENABLE ),
.C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
.C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
+ .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
.C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
+ .C_GT_REV (C_GT_REV ),
.C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
+ .C_USER_GTPOWERGOOD_DELAY_EN (C_USER_GTPOWERGOOD_DELAY_EN ),
.C_SIM_CPLL_CAL_BYPASS (C_SIM_CPLL_CAL_BYPASS ),
.C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
.C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
@@ -2333,6 +2346,8 @@ module wr_gth_wrapper_gtwizard_top #(
.C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
.C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
.C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
+ .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
+ .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
.C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
.C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
.C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),
@@ -2840,8 +2855,12 @@ module wr_gth_wrapper_gtwizard_top #(
.C_PCIE_ENABLE (C_PCIE_ENABLE ),
.C_PCIE_CORECLK_FREQ (C_PCIE_CORECLK_FREQ ),
.C_COMMON_SCALING_FACTOR (C_COMMON_SCALING_FACTOR ),
+ .C_CPLL_VCO_FREQUENCY (C_CPLL_VCO_FREQUENCY ),
.C_FREERUN_FREQUENCY (C_FREERUN_FREQUENCY ),
+ .C_GT_REV (C_GT_REV ),
.C_INCLUDE_CPLL_CAL (C_INCLUDE_CPLL_CAL ),
+ .C_ENABLE_COMMON_USRCLK (C_ENABLE_COMMON_USRCLK ),
+ .C_USER_GTPOWERGOOD_DELAY_EN (C_USER_GTPOWERGOOD_DELAY_EN ),
.C_SIM_CPLL_CAL_BYPASS (C_SIM_CPLL_CAL_BYPASS ),
.C_LOCATE_RESET_CONTROLLER (C_LOCATE_RESET_CONTROLLER ),
.C_LOCATE_USER_DATA_WIDTH_SIZING (C_LOCATE_USER_DATA_WIDTH_SIZING ),
@@ -2867,6 +2886,8 @@ module wr_gth_wrapper_gtwizard_top #(
.C_RX_USER_DATA_WIDTH (C_RX_USER_DATA_WIDTH ),
.C_TOTAL_NUM_CHANNELS (C_TOTAL_NUM_CHANNELS ),
.C_TOTAL_NUM_COMMONS (C_TOTAL_NUM_COMMONS ),
+ .C_TXPROGDIV_FREQ_ENABLE (C_TXPROGDIV_FREQ_ENABLE ),
+ .C_TXPROGDIV_FREQ_SOURCE (C_TXPROGDIV_FREQ_SOURCE ),
.C_TX_BUFFBYPASS_MODE (C_TX_BUFFBYPASS_MODE ),
.C_TX_BUFFER_BYPASS_INSTANCE_CTRL (C_TX_BUFFER_BYPASS_INSTANCE_CTRL ),
.C_TX_BUFFER_MODE (C_TX_BUFFER_MODE ),