From 744d8ee19da6c4dd91a718445f0b35556f663c79 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <g.daniluk@elproma.com.pl>
Date: Mon, 6 Feb 2012 17:07:29 +0100
Subject: [PATCH] wrcore_v2: spec_top merged with wishbonized
---
top/spec_1_1/wr_core_demo/spec_top.vhd | 33 +++++++++-----------------
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/top/spec_1_1/wr_core_demo/spec_top.vhd b/top/spec_1_1/wr_core_demo/spec_top.vhd
index 7a2a3c53..e3f71a3c 100644
--- a/top/spec_1_1/wr_core_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_core_demo/spec_top.vhd
@@ -438,10 +438,6 @@ architecture rtl of spec_top is
signal wrc_scl_i : std_logic;
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
- --signal wrc_gpio_out : std_logic_vector(7 downto 0);
- --signal wrc_gpio_in : std_logic_vector(7 downto 0);
- --signal wrc_gpio_dir : std_logic_vector(7 downto 0);
- --signal wb_adr_wrc : std_logic_vector(17 downto 0);
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
@@ -473,6 +469,9 @@ architecture rtl of spec_top is
signal wrc_slave_i : t_wishbone_slave_in;
signal wrc_slave_o : t_wishbone_slave_out;
+ signal owr_en : std_logic;
+ signal owr_i : std_logic;
+
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
component xmini_bone
@@ -734,14 +733,11 @@ begin
end if;
end process;
--- LED_RED <= std_logic(led_divider(led_divider'high));
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
- --wb_adr_wrc <= '0' & wb_adr (16 downto 0);
-
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
@@ -789,8 +785,8 @@ begin
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
- owr_en_o => open,
- owr_i => '0',
+ owr_en_o => owr_en,
+ owr_i => owr_i,
slave_i => wrc_slave_i,
slave_o => wrc_slave_o,
@@ -956,23 +952,16 @@ begin
dio_led_bot_o <= '0';
dio_out(0) <= pps;
--- dio_out(4 downto 1) <= (others => '0');
dio_oe_n_o(0) <= '0';
dio_oe_n_o(4 downto 1) <= (others => '0');
- dio_term_en_o <= (others => '0');
-
- dio_sdn_ck_n_o <= '0';
- dio_sdn_n_o <= '0';
-
- --LED_GREEN <= wrc_gpio_out(0);
- --LED_RED <= wrc_gpio_out(1);
+
+ dio_onewire_b <= '0' when owr_en = '1' else 'Z';
+ owr_i <= dio_onewire_b;
- --fpga_scl_b <= '0' when wrc_gpio_out(2) = '0' else 'Z';
- --fpga_sda_b <= '0' when wrc_gpio_out(3) = '0' else 'Z';
+ dio_term_en_o <= (others => '0');
- --wrc_gpio_in(4) <= fpga_sda_b;
- --wrc_gpio_in(5) <= '0';
- --wrc_gpio_in(6) <= button2_i;
+ dio_sdn_ck_n_o <= '1';
+ dio_sdn_n_o <= '1';
sfp_mod_def0_b <= '0';
sfp_mod_def1_b <= '0';
--
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