diff --git a/modules/fabric/xwb_fabric_sink.vhd b/modules/fabric/xwb_fabric_sink.vhd
index 978516c38fdde333e7d7538533b9ee4c128dc9d8..4f094aa7fdf4b227ec5a4106e3018d79e605d3f3 100644
--- a/modules/fabric/xwb_fabric_sink.vhd
+++ b/modules/fabric/xwb_fabric_sink.vhd
@@ -111,7 +111,7 @@ begin -- rtl
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
-
+ -- Why is there an initial stall ?
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
@@ -144,6 +144,7 @@ begin -- rtl
q_o => fout,
rd_i => rd,
almost_full_o => full,
+ full_o => open,
q_valid_o => q_valid);
p_fout_reg : process(clk_i)
@@ -181,9 +182,7 @@ use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
-
entity wb_fabric_sink is
-
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
@@ -209,33 +208,13 @@ entity wb_fabric_sink is
bytesel_o : out std_logic;
dreq_i : in std_logic
);
-
end wb_fabric_sink;
architecture wrapper of wb_fabric_sink is
-
- component xwb_fabric_sink
- port (
- clk_i : in std_logic;
- rst_n_i : in std_logic;
- snk_i : in t_wrf_sink_in;
- snk_o : out t_wrf_sink_out;
- addr_o : out std_logic_vector(1 downto 0);
- data_o : out std_logic_vector(15 downto 0);
- dvalid_o : out std_logic;
- sof_o : out std_logic;
- eof_o : out std_logic;
- error_o : out std_logic;
- bytesel_o : out std_logic;
- dreq_i : in std_logic);
- end component;
-
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
-
begin -- wrapper
-
- U_Wrapped_Sink : xwb_fabric_sink
+ U_Wrapped_Sink : entity work.xwb_fabric_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
@@ -261,5 +240,4 @@ begin -- wrapper
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
-
end wrapper;
diff --git a/modules/timing/pulse_stamper.vhd b/modules/timing/pulse_stamper.vhd
index cb715ab107dae470ff67e0a7e6135c7782c317e1..af4b736a9927769010db8b939986ac97863f9ded 100644
--- a/modules/timing/pulse_stamper.vhd
+++ b/modules/timing/pulse_stamper.vhd
@@ -68,9 +68,7 @@ end pulse_stamper;
architecture rtl of pulse_stamper is
-- Signals for input anti-metastability ffs
- signal pulse_ref : std_logic_vector(2 downto 0);
signal pulse_ref_p1 : std_logic;
- signal pulse_ref_p1_d1 : std_logic;
-- Time tagger signals
signal tag_utc_ref : std_logic_vector(39 downto 0);
@@ -85,14 +83,13 @@ architecture rtl of pulse_stamper is
-- always in the same "clock domain". This is important, e.g. for streamers,
-- in applicatinos where one WR Node works with 62.5MHz WR clock and
-- another in 125MHz.
- function f_8ns_cycle_cnt (in_cyc: std_logic_vector; ref_clk: integer)
- return std_logic_vector is
+ function f_8ns_cycle_cnt (in_cyc: std_logic_vector) return std_logic_vector is
variable out_cyc : std_logic_vector(27 downto 0);
begin
- if (ref_clk = 125000000) then
+ if g_ref_clk_rate = 125000000 then
out_cyc := in_cyc;
- elsif(ref_clk = 62500000) then
+ elsif g_ref_clk_rate = 62500000 then
out_cyc := in_cyc(26 downto 0) & '0';
else
assert FALSE report
@@ -150,7 +147,7 @@ begin -- architecture rtl
tag_valid_o <= '0';
elsif pulse_sys_p1='1' then
tag_tai_o <= tag_utc_ref;
- tag_cycles_o <= f_8ns_cycle_cnt(tag_cycles_ref,g_ref_clk_rate);
+ tag_cycles_o <= f_8ns_cycle_cnt(tag_cycles_ref);
tag_valid_o <= '1';
else
tag_valid_o <='0';
diff --git a/modules/wrc_core/wr_core.vhd b/modules/wrc_core/wr_core.vhd
index 3376aecd8821b9cd2c4dd68c03aa351ed63f2730..63c21a38591584cea7516e23154d43cb6a221524 100644
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -144,7 +144,8 @@ entity wr_core is
rst_n_i : in std_logic;
-----------------------------------------
- --Timing system
+ -- Timing system
+ -- Set helper pll and main pll DAC values
-----------------------------------------
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
diff --git a/modules/wrc_core/xwr_core.vhd b/modules/wrc_core/xwr_core.vhd
index f847391fe712b51c2068ec7153f0679c667659aa..c3665fe54a4d0a2fe1c25d7795a8f436991d74e7 100644
--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -142,7 +142,8 @@ entity xwr_core is
rst_n_i : in std_logic;
-----------------------------------------
- --Timing system
+ -- Timing system
+ -- Set helper pll and main pll DAC values
-----------------------------------------
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
@@ -222,7 +223,7 @@ entity xwr_core is
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
-----------------------------------------
- -- External WB interface
+ -- External WB interface (use clk_sys)
-- The slave port allows an external master to access WR-core registers
-- The aux_master port allows adding peripherals to the WR-core. You will
-- need to also modify the software to handle them.
@@ -234,7 +235,7 @@ entity xwr_core is
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-----------------------------------------
- -- External Fabric I/F
+ -- External Fabric I/F (use clk_sys)
-----------------------------------------
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
@@ -261,29 +262,32 @@ entity xwr_core is
fc_tx_pause_ready_o : out std_logic;
-----------------------------------------
- -- Timecode/Servo Control
+ -- Timecode/Servo Control (clk_sys)
-----------------------------------------
-
tm_link_up_o : out std_logic;
- -- DAC Control
+ -- DAC Control (for auxilliary clocks)
tm_dac_value_o : out std_logic_vector(31 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
- -- Timecode output
+
+ -- Timecode output (clk_ref)
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
- -- 1PPS output
+
+ -- 1PPS output (clk_ref)
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
+ -- Resynchronized reset (clk_sys)
rst_aux_n_o : out std_logic;
+ -- Auxillary diagnostics (used by snmp, clk_sys)
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);