diff --git a/modules/wr_endpoint/ep_registers_pkg.vhd b/modules/wr_endpoint/ep_registers_pkg.vhd
index c23c336982d87d7fce7ef27ee89d735e5425694a..9c089359bdbb15f21513cb163946e72fb47eb0d3 100644
--- a/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
--- Created : Thu Jun 9 00:58:47 2011
+-- Created : Wed Aug 10 16:10:21 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
@@ -34,10 +34,21 @@ package ep_wbgen2_pkg is
rfcr_a_hp_o : std_logic;
rfcr_keep_crc_o : std_logic;
rfcr_mru_o : std_logic_vector(13 downto 0);
- vcr_qmode_o : std_logic_vector(1 downto 0);
- vcr_fix_prio_o : std_logic;
- vcr_prio_val_o : std_logic_vector(2 downto 0);
- vcr_vid_val_o : std_logic_vector(11 downto 0);
+ vcr0_qmode_o : std_logic_vector(1 downto 0);
+ vcr0_fix_prio_o : std_logic;
+ vcr0_prio_val_o : std_logic_vector(2 downto 0);
+ vcr0_vid_val_o : std_logic_vector(11 downto 0);
+ vcr1_vid_o : std_logic_vector(11 downto 0);
+ vcr1_vid_wr_o : std_logic;
+ vcr1_value_o : std_logic;
+ vcr1_value_wr_o : std_logic;
+ pfcr_mm_addr_o : std_logic_vector(6 downto 0);
+ pfcr_mm_addr_wr_o : std_logic;
+ pfcr_mm_data_o : std_logic_vector(17 downto 0);
+ pfcr_mm_data_wr_o : std_logic;
+ pfcr_mm_write_o : std_logic;
+ pfcr_mm_write_wr_o : std_logic;
+ pfcr_enable_o : std_logic;
fcr_rxpause_o : std_logic;
fcr_txpause_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
@@ -54,9 +65,9 @@ package ep_wbgen2_pkg is
mdio_cr_data_wr_o : std_logic;
mdio_cr_addr_o : std_logic_vector(7 downto 0);
mdio_cr_rw_o : std_logic;
- mdio_sr_rdata_i : std_logic_vector(15 downto 0);
- mdio_sr_phyad_o : std_logic_vector(7 downto 0);
- mdio_sr_ready_i : std_logic;
+ mdio_asr_rdata_i : std_logic_vector(15 downto 0);
+ mdio_asr_phyad_o : std_logic_vector(7 downto 0);
+ mdio_asr_ready_i : std_logic;
dsr_lstatus_i : std_logic;
dsr_lact_o : std_logic;
dsr_lact_i : std_logic;
@@ -81,10 +92,21 @@ package ep_wbgen2_pkg is
rfcr_a_hp_o => 'Z',
rfcr_keep_crc_o => 'Z',
rfcr_mru_o => (others => 'Z'),
- vcr_qmode_o => (others => 'Z'),
- vcr_fix_prio_o => 'Z',
- vcr_prio_val_o => (others => 'Z'),
- vcr_vid_val_o => (others => 'Z'),
+ vcr0_qmode_o => (others => 'Z'),
+ vcr0_fix_prio_o => 'Z',
+ vcr0_prio_val_o => (others => 'Z'),
+ vcr0_vid_val_o => (others => 'Z'),
+ vcr1_vid_o => (others => 'Z'),
+ vcr1_vid_wr_o => 'Z',
+ vcr1_value_o => 'Z',
+ vcr1_value_wr_o => 'Z',
+ pfcr_mm_addr_o => (others => 'Z'),
+ pfcr_mm_addr_wr_o => 'Z',
+ pfcr_mm_data_o => (others => 'Z'),
+ pfcr_mm_data_wr_o => 'Z',
+ pfcr_mm_write_o => 'Z',
+ pfcr_mm_write_wr_o => 'Z',
+ pfcr_enable_o => 'Z',
fcr_rxpause_o => 'Z',
fcr_txpause_o => 'Z',
fcr_tx_thr_o => (others => 'Z'),
@@ -101,9 +123,9 @@ package ep_wbgen2_pkg is
mdio_cr_data_wr_o => 'Z',
mdio_cr_addr_o => (others => 'Z'),
mdio_cr_rw_o => 'Z',
- mdio_sr_rdata_i => (others => 'Z'),
- mdio_sr_phyad_o => (others => 'Z'),
- mdio_sr_ready_i => 'Z',
+ mdio_asr_rdata_i => (others => 'Z'),
+ mdio_asr_phyad_o => (others => 'Z'),
+ mdio_asr_ready_i => 'Z',
dsr_lstatus_i => 'Z',
dsr_lact_o => 'Z',
dsr_lact_i => 'Z',
diff --git a/modules/wr_endpoint/ep_wishbone_controller.vhd b/modules/wr_endpoint/ep_wishbone_controller.vhd
index 9fa4c452398079105d3b55b7ec75646587f6865c..9c8e5ba873ca6e385b4f5bd47e4eb8a85d13f624 100644
--- a/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/modules/wr_endpoint/ep_wishbone_controller.vhd
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
--- Created : Thu Jun 9 00:58:47 2011
+-- Created : Wed Aug 10 16:10:21 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
@@ -66,10 +66,11 @@ signal ep_rfcr_a_giant_int : std_logic ;
signal ep_rfcr_a_hp_int : std_logic ;
signal ep_rfcr_keep_crc_int : std_logic ;
signal ep_rfcr_mru_int : std_logic_vector(13 downto 0);
-signal ep_vcr_qmode_int : std_logic_vector(1 downto 0);
-signal ep_vcr_fix_prio_int : std_logic ;
-signal ep_vcr_prio_val_int : std_logic_vector(2 downto 0);
-signal ep_vcr_vid_val_int : std_logic_vector(11 downto 0);
+signal ep_vcr0_qmode_int : std_logic_vector(1 downto 0);
+signal ep_vcr0_fix_prio_int : std_logic ;
+signal ep_vcr0_prio_val_int : std_logic_vector(2 downto 0);
+signal ep_vcr0_vid_val_int : std_logic_vector(11 downto 0);
+signal ep_pfcr_enable_int : std_logic ;
signal ep_fcr_rxpause_int : std_logic ;
signal ep_fcr_txpause_int : std_logic ;
signal ep_fcr_tx_thr_int : std_logic_vector(7 downto 0);
@@ -80,7 +81,7 @@ signal ep_dmcr_en_int : std_logic ;
signal ep_dmcr_n_avg_int : std_logic_vector(11 downto 0);
signal ep_mdio_cr_addr_int : std_logic_vector(7 downto 0);
signal ep_mdio_cr_rw_int : std_logic ;
-signal ep_mdio_sr_phyad_int : std_logic_vector(7 downto 0);
+signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
signal ep_rmon_ram_rddata_int : std_logic_vector(31 downto 0);
signal ep_rmon_ram_rd_int : std_logic ;
signal ep_rmon_ram_wr_int : std_logic ;
@@ -127,10 +128,16 @@ begin
ep_rfcr_a_hp_int <= '0';
ep_rfcr_keep_crc_int <= '0';
ep_rfcr_mru_int <= "00000000000000";
- ep_vcr_qmode_int <= "00";
- ep_vcr_fix_prio_int <= '0';
- ep_vcr_prio_val_int <= "000";
- ep_vcr_vid_val_int <= "000000000000";
+ ep_vcr0_qmode_int <= "00";
+ ep_vcr0_fix_prio_int <= '0';
+ ep_vcr0_prio_val_int <= "000";
+ ep_vcr0_vid_val_int <= "000000000000";
+ regs_b.vcr1_vid_wr_o <= '0';
+ regs_b.vcr1_value_wr_o <= '0';
+ regs_b.pfcr_mm_addr_wr_o <= '0';
+ regs_b.pfcr_mm_data_wr_o <= '0';
+ regs_b.pfcr_mm_write_wr_o <= '0';
+ ep_pfcr_enable_int <= '0';
ep_fcr_rxpause_int <= '0';
ep_fcr_txpause_int <= '0';
ep_fcr_tx_thr_int <= "00000000";
@@ -143,7 +150,7 @@ begin
regs_b.mdio_cr_data_wr_o <= '0';
ep_mdio_cr_addr_int <= "00000000";
ep_mdio_cr_rw_int <= '0';
- ep_mdio_sr_phyad_int <= "00000000";
+ ep_mdio_asr_phyad_int <= "00000000";
regs_b.dsr_lact_load_o <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
@@ -152,6 +159,11 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ep_ecr_rst_cnt_int <= '0';
+ regs_b.vcr1_vid_wr_o <= '0';
+ regs_b.vcr1_value_wr_o <= '0';
+ regs_b.pfcr_mm_addr_wr_o <= '0';
+ regs_b.pfcr_mm_data_wr_o <= '0';
+ regs_b.pfcr_mm_write_wr_o <= '0';
regs_b.dmsr_ps_rdy_load_o <= '0';
regs_b.mdio_cr_data_wr_o <= '0';
regs_b.dsr_lact_load_o <= '0';
@@ -159,6 +171,11 @@ begin
else
ep_tscr_cs_start_int <= ep_tscr_cs_start_int_delay;
ep_tscr_cs_start_int_delay <= '0';
+ regs_b.vcr1_vid_wr_o <= '0';
+ regs_b.vcr1_value_wr_o <= '0';
+ regs_b.pfcr_mm_addr_wr_o <= '0';
+ regs_b.pfcr_mm_data_wr_o <= '0';
+ regs_b.pfcr_mm_write_wr_o <= '0';
regs_b.dmsr_ps_rdy_load_o <= '0';
regs_b.mdio_cr_data_wr_o <= '0';
regs_b.dsr_lact_load_o <= '0';
@@ -278,15 +295,15 @@ begin
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
- ep_vcr_qmode_int <= wrdata_reg(1 downto 0);
- ep_vcr_fix_prio_int <= wrdata_reg(2);
- ep_vcr_prio_val_int <= wrdata_reg(6 downto 4);
- ep_vcr_vid_val_int <= wrdata_reg(27 downto 16);
+ ep_vcr0_qmode_int <= wrdata_reg(1 downto 0);
+ ep_vcr0_fix_prio_int <= wrdata_reg(2);
+ ep_vcr0_prio_val_int <= wrdata_reg(6 downto 4);
+ ep_vcr0_vid_val_int <= wrdata_reg(27 downto 16);
else
- rddata_reg(1 downto 0) <= ep_vcr_qmode_int;
- rddata_reg(2) <= ep_vcr_fix_prio_int;
- rddata_reg(6 downto 4) <= ep_vcr_prio_val_int;
- rddata_reg(27 downto 16) <= ep_vcr_vid_val_int;
+ rddata_reg(1 downto 0) <= ep_vcr0_qmode_int;
+ rddata_reg(2) <= ep_vcr0_fix_prio_int;
+ rddata_reg(6 downto 4) <= ep_vcr0_prio_val_int;
+ rddata_reg(27 downto 16) <= ep_vcr0_vid_val_int;
rddata_reg(3) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
@@ -305,6 +322,88 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
+ if (wb_we_i = '1') then
+ regs_b.vcr1_vid_wr_o <= '1';
+ regs_b.vcr1_value_wr_o <= '1';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "0101" =>
+ if (wb_we_i = '1') then
+ regs_b.pfcr_mm_addr_wr_o <= '1';
+ regs_b.pfcr_mm_data_wr_o <= '1';
+ regs_b.pfcr_mm_write_wr_o <= '1';
+ ep_pfcr_enable_int <= wrdata_reg(26);
+ else
+ rddata_reg(26) <= ep_pfcr_enable_int;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "0110" =>
if (wb_we_i = '1') then
ep_fcr_rxpause_int <= wrdata_reg(0);
ep_fcr_txpause_int <= wrdata_reg(1);
@@ -324,7 +423,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "0101" =>
+ when "0111" =>
if (wb_we_i = '1') then
ep_mach_int <= wrdata_reg(15 downto 0);
else
@@ -348,7 +447,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "0110" =>
+ when "1000" =>
if (wb_we_i = '1') then
ep_macl_int <= wrdata_reg(31 downto 0);
else
@@ -356,7 +455,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "0111" =>
+ when "1001" =>
if (wb_we_i = '1') then
ep_dmcr_en_int <= wrdata_reg(0);
ep_dmcr_n_avg_int <= wrdata_reg(27 downto 16);
@@ -385,7 +484,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "1000" =>
+ when "1010" =>
if (wb_we_i = '1') then
regs_b.dmsr_ps_rdy_load_o <= '1';
else
@@ -401,7 +500,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "1001" =>
+ when "1011" =>
if (wb_we_i = '1') then
regs_b.mdio_cr_data_wr_o <= '1';
ep_mdio_cr_addr_int <= wrdata_reg(23 downto 16);
@@ -435,13 +534,13 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "1010" =>
+ when "1100" =>
if (wb_we_i = '1') then
- ep_mdio_sr_phyad_int <= wrdata_reg(23 downto 16);
+ ep_mdio_asr_phyad_int <= wrdata_reg(23 downto 16);
else
- rddata_reg(15 downto 0) <= regs_b.mdio_sr_rdata_i;
- rddata_reg(23 downto 16) <= ep_mdio_sr_phyad_int;
- rddata_reg(31) <= regs_b.mdio_sr_ready_i;
+ rddata_reg(15 downto 0) <= regs_b.mdio_asr_rdata_i;
+ rddata_reg(23 downto 16) <= ep_mdio_asr_phyad_int;
+ rddata_reg(31) <= regs_b.mdio_asr_ready_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
@@ -452,14 +551,14 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "1011" =>
+ when "1101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= "11001010111111101011101010111110";
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "1100" =>
+ when "1110" =>
if (wb_we_i = '1') then
regs_b.dsr_lact_load_o <= '1';
else
@@ -615,13 +714,30 @@ regs_b.rfcr_keep_crc_o <= ep_rfcr_keep_crc_int;
-- Maximum receive unit (MRU)
regs_b.rfcr_mru_o <= ep_rfcr_mru_int;
-- RX 802.1q port mode
-regs_b.vcr_qmode_o <= ep_vcr_qmode_int;
+regs_b.vcr0_qmode_o <= ep_vcr0_qmode_int;
-- Force 802.1q priority
-regs_b.vcr_fix_prio_o <= ep_vcr_fix_prio_int;
--- Port-assigned 802.1x priority
-regs_b.vcr_prio_val_o <= ep_vcr_prio_val_int;
+regs_b.vcr0_fix_prio_o <= ep_vcr0_fix_prio_int;
+-- Port-assigned 802.1q priority
+regs_b.vcr0_prio_val_o <= ep_vcr0_prio_val_int;
-- Port-assigned VID
-regs_b.vcr_vid_val_o <= ep_vcr_vid_val_int;
+regs_b.vcr0_vid_val_o <= ep_vcr0_vid_val_int;
+-- Port untagged set bitmap VID
+-- pass-through field: Port untagged set bitmap VID in register: VLAN Control Register 1
+regs_b.vcr1_vid_o <= wrdata_reg(11 downto 0);
+-- Port untagged set bitmap value
+-- pass-through field: Port untagged set bitmap value in register: VLAN Control Register 1
+regs_b.vcr1_value_o <= wrdata_reg(12);
+-- Microcode Memory Address
+-- pass-through field: Microcode Memory Address in register: Packet Filter Control Register
+regs_b.pfcr_mm_addr_o <= wrdata_reg(6 downto 0);
+-- Microcode Memory Data (half-word)
+-- pass-through field: Microcode Memory Data (half-word) in register: Packet Filter Control Register
+regs_b.pfcr_mm_data_o <= wrdata_reg(24 downto 7);
+-- Microcode Memory Write Enable
+-- pass-through field: Microcode Memory Write Enable in register: Packet Filter Control Register
+regs_b.pfcr_mm_write_o <= wrdata_reg(25);
+-- Packet Filter Enable
+regs_b.pfcr_enable_o <= ep_pfcr_enable_int;
-- RX Pause enable
regs_b.fcr_rxpause_o <= ep_fcr_rxpause_int;
-- TX Pause enable
@@ -650,7 +766,7 @@ regs_b.mdio_cr_addr_o <= ep_mdio_cr_addr_int;
regs_b.mdio_cr_rw_o <= ep_mdio_cr_rw_int;
-- MDIO Read Value
-- MDIO PHY Address
-regs_b.mdio_sr_phyad_o <= ep_mdio_sr_phyad_int;
+regs_b.mdio_asr_phyad_o <= ep_mdio_asr_phyad_int;
-- MDIO Ready
-- Link status
-- Link activity
diff --git a/modules/wr_endpoint/ep_wishbone_controller.wb b/modules/wr_endpoint/ep_wishbone_controller.wb
index 30bf0d2de3e6a3398f5003c15e88a822a01fa6db..993b3aac1d818451dbed4e6fd524e1a6ce24f188 100644
--- a/modules/wr_endpoint/ep_wishbone_controller.wb
+++ b/modules/wr_endpoint/ep_wishbone_controller.wb
@@ -117,7 +117,7 @@ peripheral {
field {
name = "Receive timestamping enable";
- description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface\
+ description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface. Must be enabled if used in a multi-port configuration (e.g. in a switch)\
0: disables RX timestamping";
prefix = "EN_RXTS";
access_bus = READ_WRITE;
@@ -129,7 +129,7 @@ peripheral {
name = "Timestamping counter synchronization start";
prefix = "CS_START";
description = "write 1: starts synchronizing the local PPS counter used for timestamping TX/RX packets with an external pulse provided on pps_i input.\
- After synchronization, SYNC_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
+ After synchronization, the CS_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
write 0: no effect";
type = MONOSTABLE;
clock = "tx_clk_i";
@@ -203,8 +203,8 @@ peripheral {
};
reg {
- name = "VLAN control register";
- prefix = "VCR";
+ name = "VLAN control register 0";
+ prefix = "VCR0";
field {
name = "RX 802.1q port mode";
@@ -233,7 +233,7 @@ peripheral {
};
field {
- name = "Port-assigned 802.1x priority";
+ name = "Port-assigned 802.1q priority";
description = "Packet priority value for retagging. When FIX_PRIO is 1, the endpoint uses this value as the packet priority. Otherwise, priority value is taken from 802.1q header if it's present. If there is no 802.1q header, the priority is assumed to be PRIO_VAL.";
prefix = "PRIO_VAL";
type = SLV;
@@ -255,6 +255,59 @@ peripheral {
};
};
+ reg {
+ name = "VLAN Control Register 1";
+ prefix = "VCR1";
+
+ field {
+ name = "Port untagged set bitmap VID";
+ prefix = "VID";
+ type = PASS_THROUGH;
+ size = 12;
+ };
+
+ field {
+ name = "Port untagged set bitmap value";
+ prefix = "VALUE";
+ type = PASS_THROUGH;
+ size = 1;
+ };
+ };
+
+ reg {
+ name = "Packet Filter Control Register";
+ prefix = "PFCR";
+
+ field {
+ name = "Microcode Memory Address";
+ prefix = "MM_ADDR";
+ size = 7;
+ type = PASS_THROUGH;
+ };
+
+ field {
+ size = 18;
+ name = "Microcode Memory Data (half-word)";
+ prefix = "MM_DATA";
+ type = PASS_THROUGH;
+ };
+
+ field {
+ size = 1;
+ name = "Microcode Memory Write Enable";
+ prefix = "MM_WRITE";
+ type = PASS_THROUGH;
+ };
+
+ field {
+ type = BIT;
+ name = "Packet Filter Enable";
+ prefix = "ENABLE";
+ access_bus = READ_WRITE;
+ access_dev = READ_ONLY;
+ };
+ };
+
reg {
name = "Flow Control Register";
description = "";
@@ -418,7 +471,7 @@ peripheral {
reg {
name = "MDIO Address/Status Register";
description = "Register with the current status of the MDIO interface";
- prefix = "MDIO_SR";
+ prefix = "MDIO_ASR";
field {