diff --git a/board/Manifest.py b/board/Manifest.py
index 380e335ae7f00b48acb68b24e0bf2eebd9e13bf6..fca3be995c5dc195e86f80574fe37e6d82ce0532 100644
--- a/board/Manifest.py
+++ b/board/Manifest.py
@@ -1,5 +1,5 @@
try:
- if board in ["spec", "svec", "vfchd", "common"]:
+ if board in ["spec", "svec", "vfchd", "clbv2", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
diff --git a/board/clbv2/wr_clbv2_pkg.vhd b/board/clbv2/wr_clbv2_pkg.vhd
index 1185e328b60f94df6a174543256326cf2facbd33..94bdf2f03bbd4f1445cf77101a637447eb7802cb 100644
--- a/board/clbv2/wr_clbv2_pkg.vhd
+++ b/board/clbv2/wr_clbv2_pkg.vhd
@@ -282,6 +282,8 @@ package wr_clbv2_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
+ abscal_txts_o : out std_logic;
+ abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
diff --git a/syn/clbv2_ref_design/Manifest.py b/syn/clbv2_ref_design/Manifest.py
index 7d287490be7b539d503b0bc30737caaa2c07baef..2411cabdb09b59396debb6976b0856081e527662 100644
--- a/syn/clbv2_ref_design/Manifest.py
+++ b/syn/clbv2_ref_design/Manifest.py
@@ -1,3 +1,4 @@
+board = "clbv2"
target = "xilinx"
action = "synthesis"
@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
-syn_project = "clbv2_wr_ref.xise"
+syn_project = "clbv2_wr_ref.xpr"
-syn_tool = "ise"
+syn_tool = "vivado"
modules = { "local" : "../../top/clbv2_ref_design/"}
diff --git a/syn/clbv2_ref_design/clbv2_wr_ref.xise b/syn/clbv2_ref_design/clbv2_wr_ref.xise
deleted file mode 100644
index 85859b93810480cdd270a0e6dfdbffd3fa682314..0000000000000000000000000000000000000000
--- a/syn/clbv2_ref_design/clbv2_wr_ref.xise
+++ /dev/null
@@ -1,1008 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="../../modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="../../board/clbv2/xwrc_board_clbv2.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
- </file>
- <file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
- </file>
- <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
- </file>
- <file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
- </file>
- <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
- </file>
- <file xil_pn:name="../../modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
- </file>
- <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
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- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
- </file>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
- </file>
- <file xil_pn:name="../../modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
- </file>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
- </file>
- <file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
- </file>
- <file xil_pn:name="../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
- </file>
- <file xil_pn:name="../../modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
- </file>
- <file xil_pn:name="../../modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
- </file>
- <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
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- <file xil_pn:name="../../modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
- </file>
- <file xil_pn:name="../../modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
- </file>
- <file xil_pn:name="../../modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
- </file>
- <file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
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- <file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
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- <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="clbv2_wr_ref_top" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Package" xil_pn:value="fbg676" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_map.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_timesim.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_synthesis.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clbv2_wr_ref_top_translate.v" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="clbv2_wr_ref.xise" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-30T12:58:29" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9A7162D46C074C4395ECD9E6FDD4DA79" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/top/clbv2_ref_design/Manifest.py b/top/clbv2_ref_design/Manifest.py
index 7c87ee10b9e96b6e180996c73102497fc74ad6db..f0515562295566dbbb38faf119519a049b2359fc 100644
--- a/top/clbv2_ref_design/Manifest.py
+++ b/top/clbv2_ref_design/Manifest.py
@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv2_wr_ref_top.vhd",
- "clbv2_wr_ref_top.ucf",
+ "clbv2_wr_ref_top.xdc",
"clbv2_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
- "../../board/clbv2",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
diff --git a/top/clbv2_ref_design/clbv2_wr_ref_top.bmm b/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
index d394c564f48212b0e1ba2361c441d9522d5ecdf6..cd2ea4ddc7eb9411020b1da515b3e47fa5dc374c 100644
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.bmm
@@ -30,38 +30,38 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
- cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
+ cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
diff --git a/top/clbv2_ref_design/clbv2_wr_ref_top.ucf b/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
deleted file mode 100644
index fa2b9377776609cff538349279935c1b9521fd65..0000000000000000000000000000000000000000
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.ucf
+++ /dev/null
@@ -1,388 +0,0 @@
-# ---------------------------------------------------------------------------`
-# -- Clocks/resets
-# ---------------------------------------------------------------------------
-
-# -- Local oscillators
-NET "clk_20m_vcxo_i" LOC = F22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
-NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
-TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
-
-#NET "clk_125m_pllref_p_i" LOC = F6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
-#NET "clk_125m_pllref_n_i" LOC = F5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz PLL reference
-#NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
-#TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
-#NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
-#TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
-
-NET "clk_125m_gtx_p_i" LOC = D6 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
-NET "clk_125m_gtx_n_i" LOC = D5 | IOSTANDARD = "LVDS_25"; #Bank 116 -- 125 MHz GTX reference
-NET "clk_125m_gtx_p_i" TNM_NET = clk_125m_gtx_p_i;
-TIMESPEC TS_clk_125m_gtx_p_i = PERIOD "clk_125m_gtx_p_i" 8 ns HIGH 50%;
-NET "clk_125m_gtx_n_i" TNM_NET = clk_125m_gtx_n_i;
-TIMESPEC TS_clk_125m_gtx_n_i = PERIOD "clk_125m_gtx_n_i" 8 ns HIGH 50%;
-
-# ---------------------------------------------------------------------------
-# -- SPI interface to DACs
-# ---------------------------------------------------------------------------
-
-NET "pll25dac_cs_n_o" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs1
-NET "pll20dac_cs_n_o" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V -- cs2
-NET "plldac_din_o" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-NET "plldac_sclk_o" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-
-# ---------------------------------------------------------------------------
-# -- SFP I/O for transceiver
-# ---------------------------------------------------------------------------
-
-NET "sfp_txp_o" LOC = A4; #Bank 116
-NET "sfp_txn_o" LOC = A3; #Bank 116
-NET "sfp_rxp_i" LOC = B6; #Bank 116
-NET "sfp_rxn_i" LOC = B5; #Bank 116
-NET "sfp_mod_def0_i" LOC = E26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sfp detect
-NET "sfp_mod_def1_b" LOC = J26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
-NET "sfp_mod_def2_b" LOC = H26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
-NET "sfp_rate_select_o" LOC = G26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-NET "sfp_tx_fault_i" LOC = C26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-NET "sfp_tx_disable_o" LOC = D26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-NET "sfp_los_i" LOC = F25 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-
-# ---------------------------------------------------------------------------
-# -- Onewire interface
-# ---------------------------------------------------------------------------
-
-NET "onewire_b" LOC = L23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-
-# ---------------------------------------------------------------------------
-# -- UART
-# ---------------------------------------------------------------------------
-
-#TEST & DEBUG
-# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
-# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
-# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
-NET "uart_rxd_i" LOC = D19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
-NET "uart_txd_o" LOC = D20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#NET "USB_RX2" LOC = C19 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 15 VCCO - 2.5 V
-#NET "USB_TX2" LOC = B19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#USB Connection on Test&Debug Connector (J35)
-#NET "USBEXT_RX1" LOC = F14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
-#NET "USBEXT_TX1" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "USBEXT_RX2" LOC = C14 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
-#NET "USBEXT_TX2" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-
-# ---------------------------------------------------------------------------
-# -- Flash memory SPI interface
-# ---------------------------------------------------------------------------
-
-# flash_sclk_o : out std_logic;
-# flash_ncs_o : out std_logic;
-# flash_mosi_o : out std_logic;
-# flash_miso_i : in std_logic;
-
-# ---------------------------------------------------------------------------
-# -- Miscellanous CLBv2 pins
-# ---------------------------------------------------------------------------
-#NET "GPIO_LED[0]" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-NET "led_act_o" LOC = C16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D2: blinking indicates that packets are being transferred.
-#NET "GPIO_LED[1]" LOC = B16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#NET "GPIO_LED[2]" LOC = B17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#NET "GPIO_LED[3]" LOC = A17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#NET "GPIO_LED[4]" LOC = A18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-#NET "GPIO_LED[5]" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
-NET "led_link_o" LOC = A19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V -- LED D7: indicates if the link is up.
-
-NET "reset_i" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V --Reset
-
-# ---------------------------------------------------------------------------
-# -- Digital I/O FMC Pins
-# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
-# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
-# ---------------------------------------------------------------------------
-
-# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
-# -- external reference input.
-NET "dio_clk_p_i" LOC = Y22 | IOSTANDARD=LVDS_25; #CLK1_M2C_P
-NET "dio_clk_n_i" LOC = AA22 | IOSTANDARD=LVDS_25; #CLK1_M2C_N
-
-# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
-# -- the mezzanine front panel.
-NET "dio_p_i[4]" LOC = N21 | IOSTANDARD=LVDS_25; #LA00_P
-NET "dio_n_i[4]" LOC = N22 | IOSTANDARD=LVDS_25; #LA00_N
-NET "dio_p_i[3]" LOC = P16 | IOSTANDARD=LVDS_25; #LA03_P
-NET "dio_n_i[3]" LOC = N17 | IOSTANDARD=LVDS_25; #LA03_N
-NET "dio_p_i[2]" LOC = AB26 | IOSTANDARD=LVDS_25; #LA16_P
-NET "dio_n_i[2]" LOC = AC26 | IOSTANDARD=LVDS_25; #LA16_N
-NET "dio_p_i[1]" LOC = K20 | IOSTANDARD=LVDS_25; #LA20_P
-NET "dio_n_i[1]" LOC = J20 | IOSTANDARD=LVDS_25; #LA20_N
-NET "dio_p_i[0]" LOC = P19 | IOSTANDARD=LVDS_25; #LA33_P
-NET "dio_n_i[0]" LOC = P20 | IOSTANDARD=LVDS_25; #LA33_N
-
-# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
-# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
-# -- of I/O (N+1) on the front panel of the mezzanine
-NET "dio_p_o[4]" LOC = N18 | IOSTANDARD=LVDS_25; #LA04_P
-NET "dio_n_o[4]" LOC = M19 | IOSTANDARD=LVDS_25; #LA04_N
-NET "dio_p_o[3]" LOC = U19 | IOSTANDARD=LVDS_25; #LA07_P
-NET "dio_n_o[3]" LOC = U20 | IOSTANDARD=LVDS_25; #LA07_N
-NET "dio_p_o[2]" LOC = W20 | IOSTANDARD=LVDS_25; #LA08_P
-NET "dio_n_o[2]" LOC = Y21 | IOSTANDARD=LVDS_25; #LA08_N
-NET "dio_p_o[1]" LOC = M21 | IOSTANDARD=LVDS_25; #LA28_P
-NET "dio_n_o[1]" LOC = M22 | IOSTANDARD=LVDS_25; #LA28_N
-NET "dio_p_o[0]" LOC = N19 | IOSTANDARD=LVDS_25; #LA29_P
-NET "dio_n_o[0]" LOC = M20 | IOSTANDARD=LVDS_25; #LA29_N
-
-# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
-# -- panel is configured as an output.
-NET "dio_oe_n_o[4]" LOC = AE22 | IOSTANDARD=LVCMOS25; #LA05_P
-NET "dio_oe_n_o[3]" LOC = U26 | IOSTANDARD=LVCMOS25; #LA11_P
-NET "dio_oe_n_o[2]" LOC = AB25 | IOSTANDARD=LVCMOS25; #LA15_N
-NET "dio_oe_n_o[1]" LOC = N23 | IOSTANDARD=LVCMOS25; #LA24_N
-NET "dio_oe_n_o[0]" LOC = P24 | IOSTANDARD=LVCMOS25; #LA30_P
-
-# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
-# -- panel is 50-ohm terminated
-NET "dio_term_en_o[4]" LOC = P25 | IOSTANDARD=LVCMOS25; #LA09_N
-NET "dio_term_en_o[3]" LOC = R25 | IOSTANDARD=LVCMOS25; #LA09_P
-NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25; #LA05_N
-NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25; #LA06_N
-NET "dio_term_en_o[0]" LOC = N24 | IOSTANDARD=LVCMOS25; #LA30_N
-
-# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
-# -- blink 1-PPS.
-NET "dio_led_top_o" LOC = R21 | IOSTANDARD=LVCMOS25; #LA01_P
-NET "dio_led_bot_o" LOC = P21 | IOSTANDARD=LVCMOS25; #LA01_N
-
-# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
-# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
-NET "dio_scl_b" LOC = D24 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-NET "dio_sda_b" LOC = D23 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-
-# ---------------------------------------------------------------------------
-# -- GPIO connector
-# ---------------------------------------------------------------------------
-#NET "GPIO[1]" LOC = H8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[2]" LOC = J8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[3]" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[4]" LOC = H9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[5]" LOC = F8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[6]" LOC = G10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[7]" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[8]" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[9]" LOC = D9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[10]" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[11]" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[12]" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[13]" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[14]" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[15]" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "GPIO[16]" LOC = B10 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-
-#FMC SIGNALS CLK LPC
-#NET "FMC_CLK0_M2C_P" LOC = Y23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_CLK0_M2C_N" LOC = AA24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_CLK1_M2C_P" LOC = Y22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_CLK1_M2C_N" LOC = AA22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA00_CC_P" LOC = N21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA00_CC_N" LOC = N22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA01_CC_P" LOC = R21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA01_CC_N" LOC = P21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA17_CC_P" LOC = R22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA17_CC_N" LOC = R23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA18_CC_P" LOC = AA23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA18_CC_N" LOC = AB24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-
-#FMC SIGNALS CLK HPC
-#NET "FMC_HA00_CC_P" LOC = AC23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA00_CC_N" LOC = AC24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA01_CC_P" LOC = F17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA01_CC_N" LOC = E17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA17_CC_P" LOC = E18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA17_CC_N" LOC = D18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-
-########################################################
-
-#FMC SIGNALS LPC
-#NET "FMC_PRSNT_B" LOC = K21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
-#NET "FMC_LA02_P" LOC = H19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA02_N" LOC = G20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA03_P" LOC = P16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA03_N" LOC = N17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA04_P" LOC = N18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA04_N" LOC = M19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA05_P" LOC = AE22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA05_N" LOC = AF22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 23
-#NET "FMC_LA06_P" LOC = AF24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
-#NET "FMC_LA06_N" LOC = AF25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
-#NET "FMC_LA07_P" LOC = U19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 29
-#NET "FMC_LA07_N" LOC = U20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 31
-#NET "FMC_LA08_P" LOC = W20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
-#NET "FMC_LA08_N" LOC = Y21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
-#NET "FMC_LA09_P" LOC = R25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
-#NET "FMC_LA09_N" LOC = P25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
-#NET "FMC_LA10_P" LOC = U24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA10_N" LOC = U25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA11_P" LOC = U26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA11_N" LOC = V26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA12_P" LOC = R26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA12_N" LOC = P26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA13_P" LOC = AE23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA13_N" LOC = AF23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA14_P" LOC = AD23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA14_N" LOC = AD24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA15_P" LOC = AA25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA15_N" LOC = AB25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA16_P" LOC = AB26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA16_N" LOC = AC26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA19_P" LOC = W23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38
-#NET "FMC_LA19_N" LOC = W24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40
-#NET "FMC_LA20_P" LOC = K20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA20_N" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA21_P" LOC = M25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA21_N" LOC = L25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA22_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA22_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_LA23_P" LOC = K25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA23_N" LOC = K26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA24_P" LOC = P23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA24_N" LOC = N23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA25_P" LOC = N26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA25_N" LOC = M26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA26_P" LOC = T22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA26_N" LOC = T23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA27_P" LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA27_N" LOC = V24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_LA28_P" LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA28_N" LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA29_P" LOC = N19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA29_N" LOC = M20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA30_P" LOC = P24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA30_N" LOC = N24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA31_P" LOC = M24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA31_N" LOC = L24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA32_P" LOC = T20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA32_N" LOC = R20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA33_P" LOC = P19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_LA33_N" LOC = P20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-
-#FMC SIGNALS HPC
-#NET "FMC_HA02_P" LOC = J18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA02_N" LOC = J19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA03_P" LOC = G19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA03_N" LOC = F20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA04_P" LOC = F19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA04_N" LOC = E20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA05_P" LOC = H17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA05_N" LOC = H18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA06_P" LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA06_N" LOC = K17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA07_P" LOC = M17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA07_N" LOC = L18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA08_P" LOC = R16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA08_N" LOC = R17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA09_P" LOC = R18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA09_N" LOC = P18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA10_P" LOC = T18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA10_N" LOC = T19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA11_P" LOC = U17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA11_N" LOC = T17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA12_P" LOC = AB21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA12_N" LOC = AC21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA13_P" LOC = AD21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA13_N" LOC = AE21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA14_P" LOC = V21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA14_N" LOC = W21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA15_P" LOC = U22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA15_N" LOC = V22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA16_P" LOC = T24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA16_N" LOC = T25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V
-#NET "FMC_HA18_P" LOC = W25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA18_N" LOC = W26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA19_P" LOC = AD26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA19_N" LOC = AE26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA20_P" LOC = AD25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA20_N" LOC = AE25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA21_P" LOC = Y25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA21_N" LOC = Y26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA22_P" LOC = AB22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA22_N" LOC = AC22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 12 VCCO - 2.5 V
-#NET "FMC_HA23_P" LOC = L17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-#NET "FMC_HA23_N" LOC = K18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V
-
-#OCTOPUS SMALL
-#NET "IIC1_SDA" LOC = J13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "IIC1_SCL" LOC = H13 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "EN_SCLK" LOC = H12 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "PMT_P[0]" LOC = AD16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[0]" LOC = AE16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[1]" LOC = Y17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[1]" LOC = Y18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[2]" LOC = W18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[2]" LOC = W19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[3]" LOC = AD15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[3]" LOC = AE15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[4]" LOC = AA17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[4]" LOC = AA18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[5]" LOC = AA19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[5]" LOC = AA20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[6]" LOC = AC14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[6]" LOC = AD14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[7]" LOC = AC18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[7]" LOC = AD18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[8]" LOC = AB19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[8]" LOC = AB20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[9]" LOC = AF14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[9]" LOC = AF15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[10]" LOC = AB17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[10]" LOC = AC17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_P[11]" LOC = AD20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "PMT_N[11]" LOC = AE20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA0P" LOC = AE17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA0N" LOC = AF17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA1P" LOC = AE18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA1N" LOC = AF18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA2P" LOC = AF19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-#NET "SPMT_SPA2N" LOC = AF20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 32 VCCO - 1.8 V
-
-#OCTOPUS LARGE
-#NET "IIC2_SDA" LOC = H14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "IIC2_SCL" LOC = G14 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "EN_LCLK" LOC = H11 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
-#NET "PMT_P[12]" LOC = AE7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[12]" LOC = AF7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[13]" LOC = AF5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[13]" LOC = AF4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[14]" LOC = AD1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[14]" LOC = AE1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[15]" LOC = AE8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[15]" LOC = AF8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[16]" LOC = AE6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[16]" LOC = AE5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[17]" LOC = AF3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[17]" LOC = AF2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[18]" LOC = AC8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[18]" LOC = AD8 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[19]" LOC = AD4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[19]" LOC = AD3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[20]" LOC = AE3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[20]" LOC = AE2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[21]" LOC = AB7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[21]" LOC = AC7 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[22]" LOC = AD6 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[22]" LOC = AD5 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[23]" LOC = AB1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[23]" LOC = AC1 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[24]" LOC = AF10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[24]" LOC = AF9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[25]" LOC = AC4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[25]" LOC = AC3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[26]" LOC = AB2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[26]" LOC = AC2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[27]" LOC = AC9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[27]" LOC = AD9 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_P[28]" LOC = AA4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[28]" LOC = AB4 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[29]" LOC = AA3 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_N[29]" LOC = AA2 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 1.8 V
-#NET "PMT_P[30]" LOC = AD10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-#NET "PMT_N[30]" LOC = AE10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank 33 VCCO - 1.8 V
-
\ No newline at end of file
diff --git a/top/clbv2_ref_design/clbv2_wr_ref_top.vhd b/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
index 3a22f129774f64c5100064e930bfd5daab782070..31756327705a125433c5c51b77c345a03a5da2d2 100644
--- a/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.vhd
@@ -8,7 +8,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
--- Last update: 2017-11-08
+-- Last update: 2019-06-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CLBv2.
@@ -54,14 +54,16 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
---use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv2_wr_ref_top is
generic (
- g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
+ g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram";
+ -- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
+ -- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
+
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
@@ -125,11 +127,20 @@ entity clbv2_wr_ref_top is
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
- led_act_o : out std_logic;
+ led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
- led_link_o : out std_logic;
+ led_link_o : out std_logic;
+
+ -- Reset control
+ reset_i : in std_logic;
+ suicide : out std_logic;
- reset_i : in std_logic;
+ -- Monitoring signals output on test-pads and External Debug Connector J35
+ pll_oe_out_b : out std_logic;
+ pps_p : out std_logic;
+ pps_n : out std_logic;
+ ref_clk_p : out std_logic;
+ ref_clk_n : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
@@ -176,35 +187,6 @@ end entity clbv2_wr_ref_top;
architecture top of clbv2_wr_ref_top is
- -----------------------------------------------------------------------------
- -- Constants
- -----------------------------------------------------------------------------
-
- -- Number of masters on the wishbone crossbar
- constant c_NUM_WB_MASTERS : integer := 2;
-
- -- Number of slaves on the primary wishbone crossbar
- constant c_NUM_WB_SLAVES : integer := 1;
-
- -- Primary Wishbone master(s) offsets
- constant c_WB_MASTER_PCIE : integer := 0;
- constant c_WB_MASTER_ETHBONE : integer := 1;
-
- -- Primary Wishbone slave(s) offsets
- constant c_WB_SLAVE_WRC : integer := 0;
-
- -- sdb header address on primary crossbar
- constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-
- -- f_xwb_bridge_manual_sdb(size, sdb_addr)
- -- Note: sdb_addr is the sdb records address relative to the bridge base address
- constant c_wrc_bridge_sdb : t_sdb_bridge :=
- f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-
- -- Primary wishbone crossbar layout
- constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
- c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
@@ -248,12 +230,13 @@ architecture top of clbv2_wr_ref_top is
begin -- architecture top
+ suicide<= '1';
+ reset_n <= not reset_i; -- Reset = high active on CLB
+
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
- reset_n <= not reset_i; -- Reset = high active on CLB
-
cmp_xwrc_board_clbv2 : xwrc_board_clbv2
generic map (
g_simulation => g_simulation,
@@ -338,13 +321,13 @@ begin -- architecture top
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
- -- Configure Digital I/Os 0 to 3 as outputs
+ -- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
- -- All DIO connectors are not terminated
- dio_term_en_o <= (others => '0');
+ -- Configure Digital I/Os 3 to 4 inputs to be terminated.
+ dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
@@ -373,6 +356,21 @@ begin -- architecture top
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
+ -- Enable test-pad TP17, TP18 driver
+ pll_oe_out_b <= '0';
+
+ U_pps_mon_obuf : OBUFDS
+ port map (
+ I => wrc_pps_out,
+ O => pps_p,
+ OB => pps_n);
+
+ U_ref_clk_mon_obuf : OBUFDS
+ port map (
+ I => clk_ref_62m5,
+ O => ref_clk_p,
+ OB => ref_clk_n);
+
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
diff --git a/top/clbv2_ref_design/clbv2_wr_ref_top.xdc b/top/clbv2_ref_design/clbv2_wr_ref_top.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..e5f4f4c94440bd71934051d63da9c956712bd1f5
--- /dev/null
+++ b/top/clbv2_ref_design/clbv2_wr_ref_top.xdc
@@ -0,0 +1,659 @@
+# ---------------------------------------------------------------------------
+# -- Clocks/resets
+# ---------------------------------------------------------------------------
+
+# -- Local oscillators
+#Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
+set_property PACKAGE_PIN F22 [get_ports clk_20m_vcxo_i]
+set_property IOSTANDARD LVCMOS33 [get_ports clk_20m_vcxo_i]
+
+#Bank 116 -- 125 MHz GTX reference
+set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
+set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
+
+create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
+#create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
+
+create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
+create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
+
+set_clock_groups -asynchronous \
+-group {clk_sys } \
+-group {clk_dmtd } \
+-group {clk_20m_vcxo_i } \
+-group {clk_125m_gtx_p_i } \
+-group {RXOUTCLK} \
+-group {TXOUTCLK} \
+-group {clk_ext_mul } \
+-group {dio_clk_p_i}
+
+# ---------------------------------------------------------------------------
+# -- SPI interface to DACs
+# ---------------------------------------------------------------------------
+
+ #Bank 16 VCCO - 3.3 V
+set_property PACKAGE_PIN A13 [get_ports plldac_din_o]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o]
+set_property PACKAGE_PIN A12 [get_ports plldac_sclk_o]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o]
+set_property PACKAGE_PIN A14 [get_ports pll25dac_cs_n_o]
+set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o]
+set_property PACKAGE_PIN A15 [get_ports pll20dac_cs_n_o]
+set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o]
+
+# ---------------------------------------------------------------------------
+# -- SFP I/O for transceiver
+# ---------------------------------------------------------------------------
+
+ #Bank 116
+set_property PACKAGE_PIN A4 [get_ports sfp_txp_o]
+set_property PACKAGE_PIN A3 [get_ports sfp_txn_o]
+set_property PACKAGE_PIN B6 [get_ports sfp_rxp_i]
+set_property PACKAGE_PIN B5 [get_ports sfp_rxn_i]
+
+ #Bank 14 VCCO - 3.3 V -- sfp detect
+set_property PACKAGE_PIN E26 [get_ports sfp_mod_def0_i]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
+ #Bank 14 VCCO - 3.3 V -- scl
+set_property PACKAGE_PIN J26 [get_ports sfp_mod_def1_b]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
+ #Bank 14 VCCO - 3.3 V -- sda
+set_property PACKAGE_PIN H26 [get_ports sfp_mod_def2_b]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN G26 [get_ports sfp_rate_select_o]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN C26 [get_ports sfp_tx_fault_i]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN D26 [get_ports sfp_tx_disable_o]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN F25 [get_ports sfp_los_i]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
+
+# ---------------------------------------------------------------------------
+# -- Onewire interface
+# ---------------------------------------------------------------------------
+
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN L23 [get_ports onewire_b]
+set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
+
+# ---------------------------------------------------------------------------
+# -- UART
+# ---------------------------------------------------------------------------
+
+#TEST & DEBUG
+# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
+# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
+# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
+ #Bank 15 VCCO - 2.5 V
+set_property PACKAGE_PIN D19 [get_ports uart_rxd_i]
+set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
+set_property PULLDOWN true [get_ports uart_rxd_i]
+set_property PACKAGE_PIN D20 [get_ports uart_txd_o]
+set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
+
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN C19 [get_ports USB_RX2]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
+#set_property PULLDOWN true [get_ports USB_RX2]
+#set_property PACKAGE_PIN B19 [get_ports USB_TX2]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
+
+#USB Connection on Test&Debug Connector (J35)
+ #Bank 16 VCCO - 3.3 V
+#set_property PACKAGE_PIN F14 [get_ports USBEXT_RX1]
+#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
+#set_property PULLDOWN true [get_ports USBEXT_RX1]
+#set_property PACKAGE_PIN F13 [get_ports USBEXT_TX1]
+#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
+#set_property PACKAGE_PIN C14 [get_ports USBEXT_RX2]
+#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
+#set_property PULLDOWN true [get_ports USBEXT_RX2]
+#set_property PACKAGE_PIN C13 [get_ports USBEXT_TX2]
+#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
+
+# ---------------------------------------------------------------------------
+# -- Flash memory SPI interface
+# ---------------------------------------------------------------------------
+
+# flash_sclk_o : out std_logic;
+# flash_ncs_o : out std_logic;
+# flash_mosi_o : out std_logic;
+# flash_miso_i : in std_logic;
+
+# ---------------------------------------------------------------------------
+# -- Miscellaneous clbv2 pins
+# ---------------------------------------------------------------------------
+
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN C16 [get_ports {GPIO_LED[0]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[0]}]
+set_property PACKAGE_PIN C16 [get_ports led_act_o]
+set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
+#set_property PACKAGE_PIN B16 [get_ports {GPIO_LED[1]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[1]}]
+#set_property PACKAGE_PIN B17 [get_ports {GPIO_LED[2]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[2]}]
+#set_property PACKAGE_PIN A17 [get_ports {GPIO_LED[3]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[3]}]
+#set_property PACKAGE_PIN A18 [get_ports {GPIO_LED[4]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[4]}]
+#set_property PACKAGE_PIN A19 [get_ports {GPIO_LED[5]}]
+#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[5]}]
+set_property PACKAGE_PIN A19 [get_ports led_link_o]
+set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
+
+ #Bank 16 VCCO - 3.3 V
+set_property PACKAGE_PIN E11 [get_ports reset_i]
+set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
+
+ #Bank 15 VCCO - 2.5 V
+set_property PACKAGE_PIN K15 [get_ports suicide]
+set_property IOSTANDARD LVCMOS25 [get_ports suicide]
+
+ #Bank 16 VCCO - 3.3 V Enable test-pad TP17, TP18 driver
+set_property PACKAGE_PIN B11 [get_ports pll_oe_out_b]
+set_property IOSTANDARD LVCMOS33 [get_ports pll_oe_out_b]
+
+ #Bank 15 VCCO - 2.5 V Monitoring signals output on test-pads and External Debug Connector J35
+set_property PACKAGE_PIN C17 [get_ports pps_p]
+set_property IOSTANDARD LVDS_25 [get_ports pps_p]
+set_property PACKAGE_PIN C18 [get_ports pps_n]
+set_property IOSTANDARD LVDS_25 [get_ports pps_n]
+set_property PACKAGE_PIN D15 [get_ports ref_clk_p]
+set_property IOSTANDARD LVDS_25 [get_ports ref_clk_p]
+set_property PACKAGE_PIN D16 [get_ports ref_clk_n]
+set_property IOSTANDARD LVDS_25 [get_ports ref_clk_n]
+
+# ---------------------------------------------------------------------------
+# -- Digital I/O FMC Pins
+# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
+# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
+# ---------------------------------------------------------------------------
+
+# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
+# -- external reference input.
+ #CLK1_M2C_P
+set_property PACKAGE_PIN Y22 [get_ports dio_clk_p_i]
+set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
+ #CLK1_M2C_N
+set_property PACKAGE_PIN AA22 [get_ports dio_clk_n_i]
+set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
+
+# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
+# -- the mezzanine front panel.
+ #LA00_P
+set_property PACKAGE_PIN N21 [get_ports {dio_p_i[4]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
+ #LA00_N
+set_property PACKAGE_PIN N22 [get_ports {dio_n_i[4]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
+ #LA03_P
+set_property PACKAGE_PIN P16 [get_ports {dio_p_i[3]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
+ #LA03_N
+set_property PACKAGE_PIN N17 [get_ports {dio_n_i[3]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
+ #LA16_P
+set_property PACKAGE_PIN AB26 [get_ports {dio_p_i[2]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
+ #LA16_N
+set_property PACKAGE_PIN AC26 [get_ports {dio_n_i[2]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
+ #LA20_P
+set_property PACKAGE_PIN K20 [get_ports {dio_p_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
+ #LA20_N
+set_property PACKAGE_PIN J20 [get_ports {dio_n_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
+ #LA33_P
+set_property PACKAGE_PIN P19 [get_ports {dio_p_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
+ #LA33_N
+set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
+
+
+# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
+# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
+# -- of I/O (N+1) on the front panel of the mezzanine
+ #LA04_P
+set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
+ #LA04_N
+set_property PACKAGE_PIN M19 [get_ports {dio_n_o[4]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
+ #LA07_P
+set_property PACKAGE_PIN U19 [get_ports {dio_p_o[3]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
+ #LA07_N
+set_property PACKAGE_PIN U20 [get_ports {dio_n_o[3]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
+ #LA08_P
+set_property PACKAGE_PIN W20 [get_ports {dio_p_o[2]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
+ #LA08_N
+set_property PACKAGE_PIN Y21 [get_ports {dio_n_o[2]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
+ #LA28_P
+set_property PACKAGE_PIN M21 [get_ports {dio_p_o[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
+ #LA28_N
+set_property PACKAGE_PIN M22 [get_ports {dio_n_o[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
+ #LA29_P
+set_property PACKAGE_PIN N19 [get_ports {dio_p_o[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
+ #LA29_N
+set_property PACKAGE_PIN M20 [get_ports {dio_n_o[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
+
+# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
+# -- panel is configured as an output.
+#LA05_P
+set_property PACKAGE_PIN AE22 [get_ports {dio_oe_n_o[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
+ #LA11_P
+set_property PACKAGE_PIN U26 [get_ports {dio_oe_n_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
+ #LA15_N
+set_property PACKAGE_PIN AB25 [get_ports {dio_oe_n_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
+ #LA24_N
+set_property PACKAGE_PIN N23 [get_ports {dio_oe_n_o[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
+ #LA30_P
+set_property PACKAGE_PIN P24 [get_ports {dio_oe_n_o[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
+
+# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
+# -- panel is 50-ohm terminated
+ #LA09_N
+set_property PACKAGE_PIN P25 [get_ports {dio_term_en_o[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
+ #LA09_P
+set_property PACKAGE_PIN R25 [get_ports {dio_term_en_o[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
+ #LA05_N
+set_property PACKAGE_PIN AF22 [get_ports {dio_term_en_o[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
+ #LA06_N
+set_property PACKAGE_PIN AF25 [get_ports {dio_term_en_o[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
+ #LA30_N
+set_property PACKAGE_PIN N24 [get_ports {dio_term_en_o[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
+
+# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
+# -- blink 1-PPS.
+ #LA01_P
+set_property PACKAGE_PIN R21 [get_ports dio_led_top_o]
+set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
+ #LA01_N
+set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
+set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
+
+# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
+# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
+ #Bank 14 VCCO - 3.3 V
+set_property PACKAGE_PIN D24 [get_ports dio_scl_b]
+set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
+set_property PACKAGE_PIN D23 [get_ports dio_sda_b]
+set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
+
+# ---------------------------------------------------------------------------
+# -- GPIO connector
+# ---------------------------------------------------------------------------
+ #Bank 16 VCCO - 3.3 V
+#set_property PACKAGE_PIN H8 [get_ports {GPIO[1]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[1]}]
+#set_property PACKAGE_PIN J8 [get_ports {GPIO[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[2]}]
+#set_property PACKAGE_PIN G9 [get_ports {GPIO[3]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[3]}]
+#set_property PACKAGE_PIN H9 [get_ports {GPIO[4]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[4]}]
+#set_property PACKAGE_PIN F8 [get_ports {GPIO[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[5]}]
+#set_property PACKAGE_PIN G10 [get_ports {GPIO[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[6]}]
+#set_property PACKAGE_PIN F9 [get_ports {GPIO[7]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[7]}]
+#set_property PACKAGE_PIN F10 [get_ports {GPIO[8]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[8]}]
+#set_property PACKAGE_PIN D9 [get_ports {GPIO[9]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[9]}]
+#set_property PACKAGE_PIN D8 [get_ports {GPIO[10]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[10]}]
+#set_property PACKAGE_PIN B9 [get_ports {GPIO[11]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[11]}]
+#set_property PACKAGE_PIN C9 [get_ports {GPIO[12]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[12]}]
+#set_property PACKAGE_PIN A9 [get_ports {GPIO[13]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[13]}]
+#set_property PACKAGE_PIN A8 [get_ports {GPIO[14]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[14]}]
+#set_property PACKAGE_PIN A10 [get_ports {GPIO[15]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[15]}]
+#set_property PACKAGE_PIN B10 [get_ports {GPIO[16]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO[16]}]
+
+#FMC SIGNALS CLK LPC
+ #Bank 12 VCCO - 2.5 V
+#set_property PACKAGE_PIN Y23 [get_ports FMC_CLK0_M2C_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_P]
+#set_property PACKAGE_PIN AA24 [get_ports FMC_CLK0_M2C_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_N]
+#set_property PACKAGE_PIN Y22 [get_ports FMC_CLK1_M2C_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_P]
+#set_property PACKAGE_PIN AA22 [get_ports FMC_CLK1_M2C_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_N]
+
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 1
+#set_property PACKAGE_PIN N21 [get_ports FMC_LA00_CC_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 3
+#set_property PACKAGE_PIN N22 [get_ports FMC_LA00_CC_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
+#set_property PACKAGE_PIN R21 [get_ports FMC_LA01_CC_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
+#set_property PACKAGE_PIN P21 [get_ports FMC_LA01_CC_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 30
+#set_property PACKAGE_PIN R22 [get_ports FMC_LA17_CC_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
+#set_property PACKAGE_PIN R23 [get_ports FMC_LA17_CC_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
+#set_property PACKAGE_PIN AA23 [get_ports FMC_LA18_CC_P]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_P]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
+#set_property PACKAGE_PIN AB24 [get_ports FMC_LA18_CC_N]
+#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_N]
+#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_N]
+
+########################################################
+
+#FMC SIGNALS LPC
+ #Bank 14 VCCO - 3.3 V
+#set_property PACKAGE_PIN K21 [get_ports FMC_PRSNT_B]
+#set_property IOSTANDARD LVCMOS33 [get_ports FMC_PRSNT_B]
+ #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
+#set_property PACKAGE_PIN H19 [get_ports FMC_LA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_P]
+ #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
+#set_property PACKAGE_PIN G20 [get_ports FMC_LA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 13
+#set_property PACKAGE_PIN P16 [get_ports FMC_LA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 15
+#set_property PACKAGE_PIN N17 [get_ports FMC_LA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 17
+#set_property PACKAGE_PIN N18 [get_ports FMC_LA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 19
+#set_property PACKAGE_PIN M19 [get_ports FMC_LA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 21
+#set_property PACKAGE_PIN AE22 [get_ports FMC_LA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 23
+#set_property PACKAGE_PIN AF22 [get_ports FMC_LA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
+#set_property PACKAGE_PIN AF24 [get_ports FMC_LA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
+#set_property PACKAGE_PIN AF25 [get_ports FMC_LA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 29
+#set_property PACKAGE_PIN U19 [get_ports FMC_LA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 31
+#set_property PACKAGE_PIN U20 [get_ports FMC_LA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
+#set_property PACKAGE_PIN W20 [get_ports FMC_LA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
+#set_property PACKAGE_PIN Y21 [get_ports FMC_LA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
+#set_property PACKAGE_PIN R25 [get_ports FMC_LA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
+#set_property PACKAGE_PIN P25 [get_ports FMC_LA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
+#set_property PACKAGE_PIN U24 [get_ports FMC_LA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
+#set_property PACKAGE_PIN U25 [get_ports FMC_LA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 6
+#set_property PACKAGE_PIN U26 [get_ports FMC_LA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
+#set_property PACKAGE_PIN V26 [get_ports FMC_LA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_N]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
+#set_property PACKAGE_PIN R26 [get_ports FMC_LA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_P]
+ #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
+#set_property PACKAGE_PIN P26 [get_ports FMC_LA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
+#set_property PACKAGE_PIN AE23 [get_ports FMC_LA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
+#set_property PACKAGE_PIN AF23 [get_ports FMC_LA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
+#set_property PACKAGE_PIN AD23 [get_ports FMC_LA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
+#set_property PACKAGE_PIN AD24 [get_ports FMC_LA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
+#set_property PACKAGE_PIN AA25 [get_ports FMC_LA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 24
+#set_property PACKAGE_PIN AB25 [get_ports FMC_LA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 26
+#set_property PACKAGE_PIN AB26 [get_ports FMC_LA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 28
+#set_property PACKAGE_PIN AC26 [get_ports FMC_LA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_N]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
+#set_property PACKAGE_PIN W23 [get_ports FMC_LA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_P]
+ #Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
+#set_property PACKAGE_PIN W24 [get_ports FMC_LA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_N]
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN K20 [get_ports FMC_LA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_P]
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN J20 [get_ports FMC_LA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M25 [get_ports FMC_LA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN L25 [get_ports FMC_LA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_N]
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN L19 [get_ports FMC_LA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_P]
+ #Bank 15 VCCO - 2.5 V
+#set_property PACKAGE_PIN L20 [get_ports FMC_LA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN K25 [get_ports FMC_LA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN K26 [get_ports FMC_LA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN P23 [get_ports FMC_LA24_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN N23 [get_ports FMC_LA24_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN N26 [get_ports FMC_LA25_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M26 [get_ports FMC_LA25_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN T22 [get_ports FMC_LA26_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN T23 [get_ports FMC_LA26_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_N]
+ #Bank 12 VCCO - 2.5 V
+#set_property PACKAGE_PIN V23 [get_ports FMC_LA27_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_P]
+ #Bank 12 VCCO - 2.5 V
+#set_property PACKAGE_PIN V24 [get_ports FMC_LA27_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M21 [get_ports FMC_LA28_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M22 [get_ports FMC_LA28_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN N19 [get_ports FMC_LA29_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M20 [get_ports FMC_LA29_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN P24 [get_ports FMC_LA30_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN N24 [get_ports FMC_LA30_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN M24 [get_ports FMC_LA31_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN L24 [get_ports FMC_LA31_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN T20 [get_ports FMC_LA32_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN R20 [get_ports FMC_LA32_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_N]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN P19 [get_ports FMC_LA33_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_P]
+ #Bank 13 VCCO - 2.5 V
+#set_property PACKAGE_PIN P20 [get_ports FMC_LA33_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_N]
+
+#OCTOPUS SMALL
+#NET "IIC1_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
+#NET "IIC1_SCL" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
+#NET "EN_SCLK" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[0]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[0]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[1]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[1]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[2]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[2]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[3]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[3]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[4]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[4]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[5]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[5]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[6]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[6]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[7]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[7]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[8]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[8]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[9]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[9]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[10]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[10]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[11]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[11]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA0P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA0N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA1P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA1N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA2P" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "SPMT_SPA2N" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+
+#OCTOPUS LARGE
+#NET "IIC2_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
+#NET "IIC2_SCL" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
+#NET "EN_LCLK" LOC = | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - ?.? V
+#NET "PMT_P[12]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[12]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[13]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[13]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[14]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[14]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[15]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[15]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[16]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[16]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[17]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[17]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[18]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[18]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[19]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[19]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[20]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[20]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[21]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[21]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[22]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[22]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[23]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[23]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[24]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[24]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[25]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[25]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[26]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[26]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[27]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[27]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[28]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[28]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[29]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[29]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_P[30]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+#NET "PMT_N[30]" LOC = | IOSTANDARD = LVDS | DIFF_TERM = "TRUE"; #Bank ?? VCCO - ?.? V
+
\ No newline at end of file