diff --git a/top/spec_ref_design/spec_wr_ref_top.vhd b/top/spec_ref_design/spec_wr_ref_top.vhd
index 1388cbaa61bc3bdec3f5a37d6c8c667707b1fa3a..1d3587c853ab35f1c126bba88e71f37ba0d3db6a 100644
--- a/top/spec_ref_design/spec_wr_ref_top.vhd
+++ b/top/spec_ref_design/spec_wr_ref_top.vhd
@@ -416,6 +416,7 @@ begin  -- architecture top
     generic map (
       g_simulation                => 0,
       g_with_external_clock_input => TRUE,
+      g_dpram_initf               => "../../bin/wrpc/wrc_phy8.bram",
       g_fabric_iface              => ETHERBONE)
     port map (
       areset_n_i          => areset_n,
diff --git a/top/svec_ref_design/svec_wr_ref_top.vhd b/top/svec_ref_design/svec_wr_ref_top.vhd
index cccd334739ad447a662265e856e141fa59d283fc..07c2c44e945210417c6fc13a41f6f5080766034a 100644
--- a/top/svec_ref_design/svec_wr_ref_top.vhd
+++ b/top/svec_ref_design/svec_wr_ref_top.vhd
@@ -348,6 +348,7 @@ begin  -- architecture top
   cmp_xwrc_board_svec : xwrc_board_svec
     generic map (
       g_with_external_clock_input => TRUE,
+      g_dpram_initf               => "../../bin/wrpc/wrc_phy8.bram",
       g_fabric_iface              => ETHERBONE)
     port map (
       clk_20m_vcxo_i      => clk_20m_vcxo_i,
diff --git a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
index 495f059acd48bae4b0e8d234b4b7b3dd8e3ea694..f94027b30aa2c89ecf034968faad61de08dd8944 100644
--- a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
@@ -396,6 +396,7 @@ begin  -- architecture top
   cmp_xwrc_board_vfchd : xwrc_board_vfchd
     generic map (
       g_with_external_clock_input => TRUE,
+      g_dpram_initf               => "../../bin/wrpc/wrc_phy8.mif",
       g_fabric_iface              => ETHERBONE)
     port map (
       clk_board_125m_i  => clk_board_125m_i,