wb_PatternGenerator

Digital pattern generator

Generates an user defined digital pattern. Number of pattern output bits and memory size is defined at design time. The pattern is written sequentially, the number of writes determines the pattern length.

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Pattern data input
3.2. Pattern period time
3.3. Pattern control
3.4. Pattern Status

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Pattern data input wbpattern_data_in DATA_IN
0x1 REG Pattern period time wbpattern_period PERIOD
0x2 REG Pattern control wbpattern_control CONTROL
0x3 REG Pattern Status wbpattern_status STATUS

2. HDL symbol

rst_n_i Pattern data input:
wb_clk_i wbpattern_data_in_o[31:0]
wb_addr_i[1:0] wbpattern_data_in_wr_o
wb_data_i[31:0]  
wb_data_o[31:0] Pattern period time:
wb_cyc_i wbpattern_period_period_o[31:0]
wb_sel_i[3:0]  
wb_stb_i Pattern control:
wb_we_i wbpattern_control_enable_o
wb_ack_o wbpattern_control_load_o
wbpattern_control_stop_o
wbpattern_control_stop_wr_o
wbpattern_control_softtrigger_o
wbpattern_control_softtrigger_wr_o
 
Pattern Status:
wbpattern_status_pattern_busy_i
wbpattern_status_reserved_i[14:0]
wbpattern_status_width_i[7:0]
wbpattern_status_depthbits_i[7:0]

3. Register description

3.1. Pattern data input

HW prefix: wbpattern_data_in
HW address: 0x0
C prefix: DATA_IN
C offset: 0x0

Data that defines pattern

31 30 29 28 27 26 25 24
DATA_IN[31:24]
23 22 21 20 19 18 17 16
DATA_IN[23:16]
15 14 13 12 11 10 9 8
DATA_IN[15:8]
7 6 5 4 3 2 1 0
DATA_IN[7:0]

3.2. Pattern period time

HW prefix: wbpattern_period
HW address: 0x1
C prefix: PERIOD
C offset: 0x4

Number of clock cycles for each pattern value

31 30 29 28 27 26 25 24
PERIOD[31:24]
23 22 21 20 19 18 17 16
PERIOD[23:16]
15 14 13 12 11 10 9 8
PERIOD[15:8]
7 6 5 4 3 2 1 0
PERIOD[7:0]

3.3. Pattern control

HW prefix: wbpattern_control
HW address: 0x2
C prefix: CONTROL
C offset: 0x8

Control register for pattern generator

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - SOFTTRIGGER STOP LOAD ENABLE

3.4. Pattern Status

HW prefix: wbpattern_status
HW address: 0x3
C prefix: STATUS
C offset: 0xc

Status of the pattern generator.

31 30 29 28 27 26 25 24
DEPTHBITS[7:0]
23 22 21 20 19 18 17 16
WIDTH[7:0]
15 14 13 12 11 10 9 8
RESERVED[14:7]
7 6 5 4 3 2 1 0
RESERVED[6:0] PATTERN_BUSY