1. 19 Apr, 2013 1 commit
  2. 25 Oct, 2012 1 commit
  3. 17 Jul, 2012 1 commit
  4. 27 Apr, 2010 1 commit
  5. 15 Apr, 2010 2 commits
    • cota's avatar
      Use alt_getopt to parse wbgen2's parameters · 65623b4a
      cota authored
      In the current command-line parameter parsing scheme, the
      argument comes before the positional parameters. This is against
      the UNIX tradition of passing the positional parameters first,
      and then the arguments.
      
      This patch gets rid of the existing parameter parsing code, using
      alt-getopt to do the hard work for us. This gets rid of the unusual
      behaviour mentioned above and also makes it easier to add more
      commands or synonyms of existing ones.
      
      Note: the help text has been modified to reflect these changes.
      See how the help text looks like before and after the patch:
      
      $ wbgen2 version 0.6.0
      (c) Tomasz Wlostowski/CERN BE-Co-HT 2010
      
      usage: ./wbgen2 input_file.wb [options]
      
      Options:
      -target [classic / pipelined]   - chooses between classic Wishbone bus and HT pipelined Wishbone.
      -lang   [vhdl / verilog]        - chooses the HDL language to be generated
      -vo     [file.vhdl / file.v]    - generates VHDL/Verilog code for the slave Wishbone core.
      -co     [file.h]                - generates C header file containing register definitions and access macros
      -consto [constants.v]           - generates Verilog file containing addresses of all registers/rams and writes them to specified file. Useful for writing testbenches.
      -doco   [documentation.html]    - generates nice HTML documentation and writes it to specified file.
      
      $ wbgen2 --help
      slave Wishbone generator
        wbgen2 [options] input_file.wb
      options:
        -C, --co=FILE         Write the slave's generated C header file to FILE
        -D, --doco=FILE       Write the slave's generated HTML documentation to FILE
        -h, --help              Show this help text
        -l, --lang=LANG       Set the output Hardware Description Language (HDL) to LANG
                                Valid values for LANG: {vhdl,verilog}
        -K, --constco=FILE    Populate FILE with Verilog output (mainly constants)
        -v, --version         Show version information
        -V, --vo=FILE         Write the slave's generated HDL code to FILE
      
      wbgen2 (c) Tomasz Wlostowski/CERN BE-CO-HT 2010
      Signed-off-by: Emilio G. Cota's avatarEmilio G. Cota <cota@braap.org>
      
      git-svn-id: http://svn.ohwr.org/wishbone-gen@9 4537843c-45c2-4d80-8546-c3283569414f
      65623b4a
    • cota's avatar
      Use squish to build wbgen2 · 8dfcfe1d
      cota authored
      Using squish allows us to include source files or modules into
      our generated program in a portable way.
      
      This patch changes the build procedure to use squish.
      Signed-off-by: Emilio G. Cota's avatarEmilio G. Cota <cota@braap.org>
      
      git-svn-id: http://svn.ohwr.org/wishbone-gen@7 4537843c-45c2-4d80-8546-c3283569414f
      8dfcfe1d