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Wishbone slave generator
Commit b7d4a1aa authored by Benoit Rat's avatar Benoit Rat
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bin: update squished binary (v0.7.1-epics)

parent 0cc6769f
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Showing with 515 additions and 483 deletions
wbgen2
View file @ b7d4a1aa
#!/usr/bin/env lua
package.preload['alt_getopt']=(function(...)
local n,r,u,a,o=type,pairs,ipairs,io,os
local o,s,u,a,i=type,pairs,ipairs,io,os
module("alt_getopt")
local function i(t)
local e=1
local e=#t
local e={}
for a,t in t:gmatch("(%w)(:?)")do
e[a]=#t
local function c(e)
local t=1
local t=#e
local t={}
for a,e in e:gmatch("(%w)(:?)")do
t[a]=#e
end
return e
return t
end
local function d(t,e)
a.stderr:write(t)
o.exit(e)
i.exit(e)
end
local function a(e)
d("Unknown option `-"..
......@@ -23,7 +23,7 @@ local function l(t,e)
if not t[e]then
a(e)
end
while n(t[e])=="string"do
while o(t[e])=="string"do
e=t[e]
if not t[e]then
a(e)
......@@ -31,13 +31,13 @@ end
end
return e
end
function get_ordered_opts(n,a,s)
function get_ordered_opts(n,a,r)
local t=1
local e=1
local o={}
local h={}
local i=i(a)
for t,e in r(s)do
local i=c(a)
for t,e in s(r)do
i[t]=e
end
while t<=#n do
......@@ -102,12 +102,12 @@ t=t+1
end
return o,t,h
end
function get_opts(t,o,a)
function get_opts(o,a,t)
local e={}
local a,i,t=get_ordered_opts(t,o,a)
for o,a in u(a)do
if t[o]then
e[a]=t[o]
local t,i,o=get_ordered_opts(o,a,t)
for t,a in u(t)do
if o[t]then
e[a]=o[t]
else
e[a]=1
end
......@@ -176,20 +176,20 @@ die(t.." expected.");
end
return e;
end
function range2bits(t)
local e=t[1];
local a=t[2];
local t;
if(math.abs(e)>math.abs(a))then
t=math.abs(e);
function range2bits(e)
local t=e[1];
local a=e[2];
local e;
if(math.abs(t)>math.abs(a))then
e=math.abs(t);
else
t=math.abs(a);
e=math.abs(a);
end
local t=math.ceil(math.log(t)/math.log(2));
if(e<0)then
t=t+1;
local e=math.ceil(math.log(e)/math.log(2));
if(t<0)then
e=e+1;
end
return t;
return e;
end
function calc_size(e,t)
if(e.type==MONOSTABLE or e.type==BIT)then
......@@ -214,14 +214,14 @@ die("ENUM-type fields are not yet supported. Sorry :(");
end
t.total_size=t.total_size+e.size;
end
function foreach_reg(a,t,e)
function foreach_reg(t,a,e)
if(e==nil)then
e=periph;
end
for o,e in ipairs(e)do
if(type(e)=='table')then
if(e.__type~=nil and(match(e.__type,a)))then
t(e);
if(e.__type~=nil and(match(e.__type,t)))then
a(e);
end
end
end
......@@ -285,10 +285,10 @@ function die(e)
print("Error: "..e);
os.exit(-1);
end
function match(t,e)
function match(e,t)
local a,a;
for a,e in pairs(e)do
if(t==e)then return true;end
for a,t in pairs(t)do
if(e==t)then return true;end
end
return false;
end
......@@ -296,11 +296,11 @@ function inset(t,e)
for a,e in ipairs(e)do if(t==e)then return true;end end
return false;
end
function csel(a,t,e)
if(a)then
function csel(e,t,a)
if(e)then
return t;
else
return e;
return a;
end
end
function check_field_types(e)
......@@ -324,13 +324,13 @@ return e;
end
return e;
end
function default_access(e,o,a,t)
if(e.type==o)then
function default_access(e,t,o,a)
if(e.type==t)then
if(e.access_bus==nil)then
e.access_bus=a;
e.access_bus=o;
end
if(e.access_dev==nil)then
e.access_dev=t;
e.access_dev=a;
end
end
end
......@@ -375,9 +375,9 @@ end
function log2up(e)
return math.ceil(math.log(e)/math.log(2));
end
function is_power_of_2(e)
for t=1,24 do
if(e==math.pow(2,t))then return true;end
function is_power_of_2(t)
for e=1,24 do
if(t==math.pow(2,e))then return true;end
end
return false;
end
......@@ -432,32 +432,32 @@ table.insert(t,e);
end
end
function tree_2_table(e)
local a={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(t)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
local t={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(a)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
foreach_subfield(t,function(t,o)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
foreach_subfield(a,function(a,o)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
end);
end);
return a;
return t;
end
function remove_duplicates(t)
function count_entries(t,a)
function count_entries(a,t)
local o,o,e;
e=0;
for o,t in ipairs(t)do if(t==a)then e=e+1;end end
for o,a in ipairs(a)do if(a==t)then e=e+1;end end
return e;
end
local e={};
......@@ -470,67 +470,67 @@ end
return e;
end
function wbgen_count_subblocks()
local o=0;
local a=0;
local t=0;
local e=0;
foreach_reg({TYPE_RAM},function(e)o=o+1;end);
foreach_reg({TYPE_REG},function(e)t=t+1;end);
foreach_reg({TYPE_FIFO},function(e)a=a+1;end);
foreach_reg({TYPE_IRQ},function(t)e=e+1;end);
periph.ramcount=o;
periph.fifocount=a;
periph.regcount=t;
periph.irqcount=e;
if(o+a+t+e==0)then
local t=0;
local a=0;
local o=0;
foreach_reg({TYPE_RAM},function(t)e=e+1;end);
foreach_reg({TYPE_REG},function(e)a=a+1;end);
foreach_reg({TYPE_FIFO},function(e)t=t+1;end);
foreach_reg({TYPE_IRQ},function(e)o=o+1;end);
periph.ramcount=e;
periph.fifocount=t;
periph.regcount=a;
periph.irqcount=o;
if(e+t+a+o==0)then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
function deepcopy(i)
local o={}
local function t(e)
local a={}
local function o(e)
if type(e)~="table"then
return e
elseif o[e]then
return o[e]
elseif a[e]then
return a[e]
end
local a={}
o[e]=a
for o,e in pairs(e)do
a[t(o)]=t(e)
local t={}
a[e]=t
for e,a in pairs(e)do
t[o(e)]=o(a)
end
return setmetatable(a,getmetatable(e))
return setmetatable(t,getmetatable(e))
end
return t(i)
return o(i)
end
function va(t,a)
function va(a,t)
local e={};
e.t="assign";
e.dst=t;
e.src=a;
e.dst=a;
e.src=t;
return e;
end
function vi(t,a,o)
function vi(o,a,t)
local e={};
e.t="index";
e.name=t;
e.name=o;
e.h=a;
e.l=o;
e.l=t;
return e;
end
function vinstance(t,o,a)
function vinstance(t,a,o)
local e={};
e.t="instance";
e.name=t;
e.component=o;
e.maps=a;
e.component=a;
e.maps=o;
return e;
end
function vpm(a,t)
function vpm(t,a)
local e={};
e.t="portmap";
e.to=a;
e.from=t;
e.to=t;
e.from=a;
return e;
end
function vgm(a,t)
......@@ -540,26 +540,26 @@ e.to=a;
e.from=t;
return e;
end
function vcombprocess(t,a)
function vcombprocess(a,t)
local e={};
e.t="combprocess";
e.slist=t;
e.code=a;
e.slist=a;
e.code=t;
return e;
end
function vsyncprocess(o,t,a)
function vsyncprocess(o,a,t)
local e={};
e.t="syncprocess";
e.clk=o;
e.rst=t;
e.code=a;
e.rst=a;
e.code=t;
return e;
end
function vreset(a,t)
function vreset(t,a)
local e={};
e.t="reset";
e.level=a;
e.code=t;
e.level=t;
e.code=a;
return e;
end
function vposedge(t)
......@@ -568,11 +568,11 @@ e.t="posedge";
e.code=t;
return e;
end
function vif(t,a,o)
function vif(a,t,o)
local e={};
e.t="if";
e.cond={t};
e.code=a;
e.cond={a};
e.code=t;
e.code_else=o;
return e;
end
......@@ -597,11 +597,11 @@ e.a=a;
e.b=t;
return e;
end
function vor(t,a)
function vor(a,t)
local e={};
e.t="or";
e.a=t;
e.b=a;
e.a=a;
e.b=t;
return e;
end
function vnot(t)
......@@ -610,11 +610,11 @@ e.t="not";
e.a=t;
return e;
end
function vswitch(a,t)
function vswitch(t,a)
local e={};
e.t="switch";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcase(a,t)
......@@ -659,23 +659,23 @@ local e={}
e.t="undefined";
return e;
end
function signal(o,i,a,t)
function signal(i,o,a,t)
local e={}
e.comment=t;
e.type=o;
e.range=i;
e.type=i;
e.range=o;
e.name=a;
return e;
end
VPORT_WB=1;
VPORT_REG=2;
function port(a,o,s,i,n,t)
function port(a,o,n,i,s,t)
local e={}
e.comment=n;
e.comment=s;
e.type=a;
e.range=o;
e.name=i;
e.dir=s;
e.dir=n;
if(t~=nil)then
if(t==VPORT_WB)then
e.is_wb=true;
......@@ -727,17 +727,17 @@ table_join(e,tree_2_table("ports"));
return e;
end
function cgen_build_optional_list()
local o={}
local a={}
local o={}
local e=1
for i,t in pairs(tree_2_table("optional"))do
if o[t]==nil then
o[t]=1
a[e]=t
if a[t]==nil then
a[t]=1
o[e]=t
e=e+1
end
end
return a
return o
end
function cgen_find_sigport(e)
for a,t in pairs(g_portlist)do if(e==t.name)then return t;end end
......@@ -922,17 +922,17 @@ emit("return tmp;");
emit("end function;");
emit("end package body;");
end
function cgen_vhdl_port_struct(o)
emit("type t_"..periph.hdl_prefix.."_"..o.."_registers is record");
function cgen_vhdl_port_struct(a)
emit("type t_"..periph.hdl_prefix.."_"..a.."_registers is record");
indent_right();
local a={};
local t={};
for e=1,table.getn(g_portlist)do
local e=g_portlist[e];
if(e.is_reg_port==true and e.dir==o)then
table.insert(a,e);
if(e.is_reg_port==true and e.dir==a)then
table.insert(t,e);
end
end
for t,e in ipairs(a)do
for t,e in ipairs(t)do
local t=csel(e.type==SLV and e.range==1,"std_logic",fieldtype_2_vhdl[e.type]);
local t=string.format("%-40s : %s",strip_periph_prefix(e.name),t);
if(e.range>1)then
......@@ -944,17 +944,17 @@ end
emit("end record;");
indent_left();
emit("");
emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := (");
emit("constant c_"..periph.hdl_prefix.."_"..a.."_registers_init_value: t_"..periph.hdl_prefix.."_"..a.."_registers := (");
indent_right();
for t=1,table.getn(a)do
local e=a[t];
for a=1,table.getn(t)do
local e=t[a];
line=strip_periph_prefix(e.name).." => ";
if(e.range>1)then
line=line.."(others => '0')"
else
line=line.."'0'"
end
if(t~=table.getn(a))then
if(a~=table.getn(t))then
line=line..",";
end
emit(line);
......@@ -1034,10 +1034,10 @@ if(table.getn(g_optlist)~=0)then
emit("generic (");
indent_right();
emiti()
for t,e in pairs(g_optlist)do
for e,t in pairs(g_optlist)do
emiti();
emitx(e.." : integer := 1");
if(t~=table.getn(g_optlist))then
emitx(t.." : integer := 1");
if(e~=table.getn(g_optlist))then
emit(";")
else
emit(");")
......@@ -1297,31 +1297,31 @@ emitx(") generate\n");
indent_right();recurse(e.code);indent_left();
emit("end generate "..gname..";");
end
function cgen_vhdl_not(t)
local e=node_typesize(t.a);
function cgen_vhdl_not(e)
local t=node_typesize(e.a);
emitx("not ");
if(e.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
if(t.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(e));
emitx(gen_subrange(t));
end
end
function cgen_vhdl_binary_op(e)
local a=node_typesize(e.a);
local o=node_typesize(e.b);
local t=e.t;
function cgen_vhdl_binary_op(t)
local a=node_typesize(t.a);
local o=node_typesize(t.b);
local e=t.t;
if(a.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
emitx("(");recurse({t.a});emitx(")");
else
emitx(gen_subrange(a));
end
if(t=="eq")then emitx(" = ");end
if(t=="and")then emitx(" and ");end
if(t=="or")then emitx(" or ");end
if(t=="sub")then emitx(" - ");end
if(t=="add")then emitx(" + ");end
if(e=="eq")then emitx(" = ");end
if(e=="and")then emitx(" and ");end
if(e=="or")then emitx(" or ");end
if(e=="sub")then emitx(" - ");end
if(e=="add")then emitx(" + ");end
if(o.type==EXPRESSION)then
emitx("(");recurse({e.b});emitx(")");
emitx("(");recurse({t.b});emitx(")");
else
emitx(gen_vhdl_typecvt(a,o));
end
......@@ -1356,25 +1356,25 @@ end
emit("end case;");
end
function cgen_vhdl_instance(t)
local a=0;
local o=0;
local a=0;
local e;
emit(t.name.." : "..t.component);
for t,e in pairs(t.maps)do
if(e.t=="genmap")then
o=o+1;
elseif(e.t=="portmap")then
a=a+1;
elseif(e.t=="portmap")then
o=o+1;
end
end
if(o>0)then
if(a>0)then
indent_right();
emit("generic map (");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for o,t in pairs(t.maps)do
if(t.t=="genmap")then
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==o,"",","));
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==a,"",","));
e=e+1;
end
end
......@@ -1382,15 +1382,15 @@ indent_left();
emit(")");
indent_left();
end
if(a>0)then
if(o>0)then
indent_right();
emit("port map (");
indent_right();
e=1;
for o,t in pairs(t.maps)do
for a,t in pairs(t.maps)do
if(t.t=="portmap")then
local o=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(o))..csel(e==a,"",","));
local a=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(a))..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1670,34 +1670,34 @@ indent_left();
emit("end");
end
end
function cgen_verilog_not(t)
local e=node_typesize(t.a);
function cgen_verilog_not(e)
local t=node_typesize(e.a);
emitx("! ");
if(e.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
else
emitx(gen_subrange(e));
end
end
function cgen_verilog_binary_op(e)
local a=node_typesize(e.a);
local o=node_typesize(e.b);
local t=e.t;
if(a.type==EXPRESSION)then
if(t.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(a));
emitx(gen_subrange(t));
end
if(t=="eq")then emitx(" == ");end
if(t=="and")then emitx(" && ");end
if(t=="or")then emitx(" || ");end
if(t=="sub")then emitx(" - ");end
if(t=="add")then emitx(" + ");end
end
function cgen_verilog_binary_op(t)
local o=node_typesize(t.a);
local a=node_typesize(t.b);
local e=t.t;
if(o.type==EXPRESSION)then
emitx("(");recurse({e.b});emitx(")");
emitx("(");recurse({t.a});emitx(")");
else
emitx(gen_subrange(o));
end
if(e=="eq")then emitx(" == ");end
if(e=="and")then emitx(" && ");end
if(e=="or")then emitx(" || ");end
if(e=="sub")then emitx(" - ");end
if(e=="add")then emitx(" + ");end
if(a.type==EXPRESSION)then
emitx("(");recurse({t.b});emitx(")");
else
emitx(gen_subrange(a));
end
end
function cgen_verilog_comment(e)
emitx("// "..e.str.."\n");
......@@ -1779,23 +1779,23 @@ end
function cgen_verilog_openpin(e)
emitx("");
end
function cgen_verilog_combprocess(e)
local t=true;
function cgen_verilog_combprocess(t)
local e=true;
emiti();
emitx("always @(");
a=true;
for a,e in pairs(e.slist)do
if(t)then
t=false;
for a,t in pairs(t.slist)do
if(e)then
e=false;
else
emitx(" or ");
end
emitx(e);
emitx(t);
end
emit(")");
emit("begin");
indent_right();
recurse(e.code);
recurse(t.code);
indent_left();
a=false;
emit("end");
......@@ -1833,17 +1833,17 @@ end
end
cgen_new_snippet();
cgen_verilog_header();
local e=cgen_get_snippet();
local t=cgen_get_snippet();
cgen_new_snippet();
recurse(n);
cgen_verilog_ending();
local a=cgen_get_snippet();
local e=cgen_get_snippet();
cgen_new_snippet();
cgen_verilog_module();
local t=cgen_get_snippet();
cgen_write_snippet(e);
local a=cgen_get_snippet();
cgen_write_snippet(t);
cgen_write_snippet(a);
cgen_write_snippet(e);
end
function cgen_c_field_define(e,a,o)
local t;
......@@ -1852,9 +1852,16 @@ return;
else
t=string.upper(periph.c_prefix).."_"..string.upper(a.c_prefix).."_"..string.upper(e.c_prefix);
end
if(e.nbfp==nil or e.nbfp>=e.size)then
if(e.nbfp==nil or e.nbfp>e.size)then
e.nbfp=0;
end
if(e.sign==nil)then
if(e.nbfp>0)then
e.sign=2;
else
e.sign=0;
end
end
emit("");
emit("/* definitions for field: "..e.name.." in reg: "..a.name.." */");
if(options.c_reg_style=="extended")then
......@@ -1865,16 +1872,18 @@ emit(string.format("%-45s %s","#define "..t.."_NAME","\""..e.name.."\""));
emit(string.format("%-45s %s","#define "..t.."_DESC","WBGEN2_DESC(\""..e.description:gsub("\n.*","").."\")"));
emit(string.format("%-45s %s","#define "..t.."_ACCESS","WBGEN2_"..rw_table[e.access_bus]));
emit(string.format("%-45s %d","#define "..t.."_NBFP",e.nbfp));
emit(string.format("%-45s %d","#define "..t.."_SIGN",e.sign));
emit(string.format("%-45s %d","#define "..t.."_SIZE",e.size));
if(e.type==BIT or e.type==MONOSTABLE)then
emit(string.format("%-45s %s","#define "..t.."_MASK","WBGEN2_GEN_MASK("..e.offset..", "..e.size..")"));
emit(string.format("%-45s %d","#define "..t.."_SHIFT",e.offset));
emit(string.format("%-45s %s","#define "..t.."_MASK","WBGEN2_GEN_MASK("..e.offset..", "..e.size..")"));
end
end
if(e.type==BIT or e.type==MONOSTABLE)then
emit(string.format("%-45s %s","#define "..t,"WBGEN2_GEN_MASK("..e.offset..", 1)"));
else
emit(string.format("%-45s %s","#define "..t.."_MASK","WBGEN2_GEN_MASK("..e.offset..", "..e.size..")"));
emit(string.format("%-45s %d","#define "..t.."_SHIFT",e.offset));
emit(string.format("%-45s %s","#define "..t.."_MASK","WBGEN2_GEN_MASK("..e.offset..", "..e.size..")"));
emit(string.format("%-45s %s","#define "..t.."_W(value)","WBGEN2_GEN_WRITE(value, "..e.offset..", "..e.size..")"));
if(e.type==SIGNED)then
emit(string.format("%-45s %s","#define "..t.."_R(reg)","WBGEN2_SIGN_EXTEND(WBGEN2_GEN_READ(reg, "..e.offset..", "..e.size.."), "..e.size..")"));
......@@ -1898,7 +1907,7 @@ if(e.num_fields~=nil and e.num_fields>0)then
emit("");
emit("/* definitions for register: "..e.name.." */");
t=0;
foreach_subfield(e,function(a,e)cgen_c_field_define(a,e,t);t=t+1;end);
foreach_subfield(e,function(e,a)cgen_c_field_define(e,a,t);t=t+1;end);
end
end);
foreach_reg({TYPE_RAM},function(e)
......@@ -2000,6 +2009,7 @@ if(options.c_reg_style=="extended")then
emit(string.format("%-45s %s","#define "..t.."_PREFIX","\""..e.c_prefix.."\""));
emit(string.format("%-45s %s","#define "..t.."_NAME","\""..e.name.."\""));
emit(string.format("%-45s %s","#define "..t.."_DESC","WBGEN2_DESC(\""..e.description:gsub("\n.*","").."\")"));
emit(string.format("%-45s %s","#define "..t.."_NFIELDS",e.num_fields));
end
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_REG_"..string.upper(e.c_prefix),
string.format("0x%08x",e.base*DATA_BUS_WIDTH/8)));
......@@ -2019,9 +2029,23 @@ emit("");
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIPH_PREFIX","\""..periph.c_prefix.."\""));
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIPH_NAME","\""..periph.name.."\""));
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIPH_DESC","WBGEN2_DESC(\""..periph.description:gsub("\n.*","").."\")"));
if(options.c_reg_style=="extended"and periph.sdb_vendor~=nil)then
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIPH_VENID","0x"..string.format("%016X",periph.sdb_vendor)));
emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIPH_DEVID","0x"..string.sub(md5.sumhexa(periph.hdl_entity),0,8)));
end
emit("\n#endif");
cgen_write_current_snippet();
end
function cgen_db_epics_fields(e)
if(e.epicsdb_desc==nil)then
emit(string.format("\tfield(%-5s,\"%s\")","DESC",e.name));
end
for e,t in pairs(e)do
if(type(e)=="string"and string.match(e,"epicsdb_(.*)"))then
emit(string.format("\tfield(%-5s,\"%s\")",string.upper(string.sub(e,9)),t));
end
end
end
function cgen_db_field_records(e,t,a)
local a;
if(e.c_prefix==nil)then
......@@ -2034,6 +2058,10 @@ prefix_c=t.c_prefix.."_"..e.c_prefix;
end
prefix_records=prefix_c:gsub("_(%a)",string.upper):gsub("^%l",string.upper);
end
e.precision=0
if(e.nbfp~=nil and e.nbfp>0)then
precision=math.ceil(math.log10(math.pow(2,e.nbfp)));
end
emit("##---------------- '"..e.name.."' in '"..t.name.."'");
if(e.access_bus==WRITE_ONLY or e.access_bus==READ_WRITE)then
emit("");
......@@ -2047,13 +2075,15 @@ emit(string.format("record(ao, \"$(user):%s%s\")",prefix_records,"Set"));
emit("{");
if(e.nbfp~=nil and e.nbfp>0)then
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynFloat64"));
emit(string.format("\tfield(%-5s,\"%s\")","PREC","3"));
if(e.epicsdb_prec==nil)then
emit(string.format("\tfield(%-5s,\"%d\")","PREC",precision));
end
else
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
end
emit(string.format("\tfield(%-5s,\"%s%s\")","OUT","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
end
emit(string.format("\tfield(%-5s,\"%s\")","DESC",e.name));
cgen_db_epics_fields(e);
emit("}");
end
if(e.access_bus==READ_ONLY or e.access_bus==READ_WRITE)then
......@@ -2069,14 +2099,16 @@ emit(string.format("record(ai, \"$(user):%s%s\")",prefix_records,"Rdbk"));
emit("{");
if(e.nbfp~=nil and e.nbfp>0)then
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynFloat64"));
emit(string.format("\tfield(%-5s,\"%s\")","PREC","3"));
if(e.epicsdb_prec==nil)then
emit(string.format("\tfield(%-5s,\"%d\")","PREC",precision));
end
else
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
end
emit(string.format("\tfield(%-5s,\"%s%s\")","INP","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
emit(string.format("\tfield(%-5s,\"%s\")","SCAN","I/O Intr"));
end
emit(string.format("\tfield(%-5s,\"%s\")","DESC",e.name));
cgen_db_epics_fields(e);
emit("}");
end
emit("");
......@@ -2102,7 +2134,7 @@ emit("##########################################################################
emit("# ");
emit("# * File : "..options.output_epics_db_file);
emit("# * Author : auto-generated by wbgen2 from "..input_wb_file);
emit("# * Generated : "..os.date());
emit("# * Generated : "..os.date());
emit("# ");
emit("# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE "..input_wb_file);
emit("# ");
......@@ -2170,21 +2202,21 @@ end
end
return e;
end
function htable_tdstyle(e,t,a)
tbl.data[e][t].style=a;
function htable_tdstyle(a,e,t)
tbl.data[a][e].style=t;
end
function htable_trstyle(e,a,t)
tbl.data[e].style=t;
function htable_trstyle(t,a,e)
tbl.data[t].style=e;
end
function htable_frame(o,a,t,e)
function htable_frame(o,t,a,e)
if(e==nil)then
o.data[a][t].extra='style="border: solid 1px black;"';
o.data[t][a].extra='style="border: solid 1px black;"';
else
o.data[a][t].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[a][e].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(e>t+1)then
for e=t+1,e-1 do
o.data[a][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[t][a].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[t][e].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(e>a+1)then
for e=a+1,e-1 do
o.data[t][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
end
end
end
......@@ -2222,11 +2254,11 @@ emit("</tr>");
end
emit("</table>");
end
function has_any_ports(e)
local t=false;
if(e.ports~=nil)then return true;end
foreach_subfield(e,function(e)if(e.ports~=nil)then t=true;end end);
return t;
function has_any_ports(t)
local e=false;
if(t.ports~=nil)then return true;end
foreach_subfield(t,function(t)if(t.ports~=nil)then e=true;end end);
return e;
end
function htable_add_row(e,a)
if(a>e.rows)then
......@@ -2240,8 +2272,8 @@ end
e.rows=a;
end
end
function hlink(t,e)
return'<A href="'..t..'">'..e..'</a>';
function hlink(e,t)
return'<A href="'..e..'">'..t..'</a>';
end
function hitem(e)
return'<li>'..e..'</li>';
......@@ -2250,17 +2282,17 @@ function hanchor(t,e)
return'<a name="'..t..'">'..e..'</a>';
end
doc_toc={};
function hsection(t,a,o)
function hsection(a,t,o)
local e={};
local i=0;
e.id_mangled="sect_"..t.."_"..a;
e.key=t*1e3+a;
if(a~=0)then
e.id_mangled="sect_"..a.."_"..t;
e.key=a*1e3+t;
if(t~=0)then
e.level=2;
e.id=t.."."..a..".";
e.id=a.."."..t..".";
else
e.level=1;
e.id=t..".";
e.id=a..".";
end
e.name=o;
table.insert(doc_toc,e);
......@@ -2309,44 +2341,44 @@ end
end);
cgen_doc_symbol(t);
end
function cgen_doc_mem_symbol(t)
local e={};
for t,a in pairs(t.ports)do
local t=a;
function cgen_doc_mem_symbol(a)
local t={};
for e,a in pairs(a.ports)do
local e=a;
if(string.find(a.name,"_i")~=nil)then
t.is_wb=true;
e.is_wb=true;
else
t.is_wb=false;
e.is_wb=false;
end
table.insert(e,t);
table.insert(t,e);
end
if(t.clock~=nil)then
local t=port(BIT,0,"in",t.clock);
t.is_wb=true;
table.insert(e,t);
if(a.clock~=nil)then
local e=port(BIT,0,"in",a.clock);
e.is_wb=true;
table.insert(t,e);
end
cgen_doc_symbol(e);
cgen_doc_symbol(t);
end
function cgen_doc_symbol(i)
function cgen_doc_symbol(o)
local t=htable_new(3,5);
local a=1;
local e=1;
local o=true;
for o,e in pairs(i)do
local i=true;
for o,e in pairs(o)do
if(e.is_wb)then
htable_add_row(t,a);
cgen_doc_port(t.data[a],e,true);
a=a+1;
end
end
for i,a in ipairs(i)do
for o,a in ipairs(o)do
if(type(a)=="string")then
if(o==false)then
if(i==false)then
htable_add_row(t,e);
row=t.data[e];row[3].text="&nbsp;";
e=e+1;
else
o=false;
i=false;
end
htable_add_row(t,e);
local t=t.data[e];
......@@ -2383,17 +2415,17 @@ local e=periph.description;
if(e==nil)then e="";end
emit('<p>'..string.gsub(e,"\n","<br>")..'</p>');
emit('<h3>Contents:</h3>');
table.sort(doc_toc,function(t,e)return t.key<e.key;end);
table.sort(doc_toc,function(e,t)return e.key<t.key;end);
for t,e in ipairs(doc_toc)do
emit('<span style="margin-left: '..((e.level-1)*20)..'px; ">'..e.id.." "..hlink('#'..e.id_mangled,e.name)..'</span><br/>');
end
end
function cgen_doc_memmap()
local i=0;
local o=0;
local a=2;
emit(hsection(1,0,"Memory map summary"));
local o=htable_new(1,5);
local e=o.data[1];
local i=htable_new(1,5);
local e=i.data[1];
e.is_header=true;
e[1].text="H/W Address"
e[2].text="Type";
......@@ -2402,9 +2434,9 @@ e[4].text="VHDL/Verilog prefix";
e[5].text="C prefix";
foreach_reg({TYPE_REG},function(t)
if(t.full_hdl_prefix~=nil)then
htable_add_row(o,a);
local e=o.data[a];a=a+1;
e.style=csel(i,"tr_odd","tr_even");
htable_add_row(i,a);
local e=i.data[a];a=a+1;
e.style=csel(o,"tr_odd","tr_even");
e[1].style="td_code";
e[1].text=string.format("0x%x",t.base);
if(t.doc_is_fiforeg==nil)then
......@@ -2417,14 +2449,14 @@ e[4].style="td_code";
e[4].text=t.full_hdl_prefix;
e[5].style="td_code";
e[5].text=string.upper(t.c_prefix);
i=not i;
o=not o;
end
end);
foreach_reg({TYPE_RAM},function(e)
if(e.full_hdl_prefix~=nil)then
htable_add_row(o,a);
local t=o.data[a];a=a+1;
t.style=csel(i,"tr_odd","tr_even");
htable_add_row(i,a);
local t=i.data[a];a=a+1;
t.style=csel(o,"tr_odd","tr_even");
t[1].style="td_code";
t[1].text=string.format("0x%x - 0x%x",e.base,e.base+math.pow(2,e.wrap_bits)*e.size-1);
t[2].text="MEM";
......@@ -2433,32 +2465,32 @@ t[4].style="td_code";
t[4].text=e.full_hdl_prefix;
t[5].style="td_code";
t[5].text=string.upper(e.c_prefix);
i=not i;
o=not o;
end
end);
htable_emit(o);
htable_emit(i);
end
function find_field_by_offset(e,a)
local t=nil;
foreach_subfield(e,function(e)if(a>=e.offset and a<=(e.offset+e.size-1))then t=e;end end);
return t;
function find_field_by_offset(e,t)
local a=nil;
foreach_subfield(e,function(e)if(t>=e.offset and t<=(e.offset+e.size-1))then a=e;end end);
return a;
end
function cgen_doc_fieldtable(h,i)
local e=70;
local e;
local t=1;
e=htable_new(2,8);
for t=1,8 do
e.data[1][t].style="td_bit";
e.data[1][t].text=string.format("%d",i+8-t);
local t;
local e=1;
t=htable_new(2,8);
for e=1,8 do
t.data[1][e].style="td_bit";
t.data[1][e].text=string.format("%d",i+8-e);
end
local a=i+7;
while(a>=i)do
local o=find_field_by_offset(h,a);
if(o==nil)then
e.data[2][t].style="td_unused";
e.data[2][t].text="-";
t=t+1;
t.data[2][e].style="td_unused";
t.data[2][e].text="-";
e=e+1;
a=a-1;
else
local n;
......@@ -2469,18 +2501,18 @@ n=o.offset;
end
local s=(a-n)+1;
dbg("ncells: ",s,"bit: ",a,"name: ",o.prefix);
e.data[2][t].colspan=s;
t.data[2][e].colspan=s;
local i;
i=o.c_prefix;
if(i==nil)then i=h.c_prefix;end
e.data[2][t].style="td_field";
e.data[2][t].text=csel(o.size>1,string.format("%s[%d:%d]",string.upper(i),a-o.offset,n-o.offset),string.upper(i));
htable_frame(e,2,t);
t.data[2][e].style="td_field";
t.data[2][e].text=csel(o.size>1,string.format("%s[%d:%d]",string.upper(i),a-o.offset,n-o.offset),string.upper(i));
htable_frame(t,2,e);
a=a-s;
t=t+1;
e=e+1;
end
end
htable_emit(e);
htable_emit(t);
end
function cgen_doc_access(e)
if(e==READ_ONLY)then
......@@ -2580,26 +2612,26 @@ emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
cur_irq_no=1;
function cgen_doc_irq(e)
emit(hanchor(string.upper(e.c_prefix),""));
emit(hsection(5,cur_irq_no,e.name));
function cgen_doc_irq(t)
emit(hanchor(string.upper(t.c_prefix),""));
emit(hsection(5,cur_irq_no,t.name));
cur_irq_no=cur_irq_no+1;
local t=htable_new(3,2);
t.data[1][1].text="<b>HW prefix: </b>";
t.data[2][1].text="<b>C prefix: </b>";
t.data[3][1].text="<b>Trigger: </b>";
t.data[1][2].text=string.lower(periph.hdl_prefix.."_"..e.hdl_prefix);
t.data[2][2].text=string.upper(e.c_prefix);
local e=htable_new(3,2);
e.data[1][1].text="<b>HW prefix: </b>";
e.data[2][1].text="<b>C prefix: </b>";
e.data[3][1].text="<b>Trigger: </b>";
e.data[1][2].text=string.lower(periph.hdl_prefix.."_"..t.hdl_prefix);
e.data[2][2].text=string.upper(t.c_prefix);
local a={
[EDGE_RISING]="rising edge";
[EDGE_FALLING]="falling edge";
[LEVEL_0]="low level";
[LEVEL_1]="high level";
};
t.data[3][2].text=a[e.trigger];
htable_emit(t);
if(e.description~=nil)then
emit("<p>"..string.gsub(e.description,"\n","<br>").."</p>");
e.data[3][2].text=a[t.trigger];
htable_emit(e);
if(t.description~=nil)then
emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
function cgen_generate_html_documentation()
......@@ -2608,19 +2640,19 @@ cgen_new_snippet();
emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local i=cgen_get_snippet();
local t="";
local a="";
if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks"));
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_ram(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
local a="";
local t="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit(hsection(5,0,"Interrupts"));
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_irq(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_memmap();
......@@ -2630,8 +2662,8 @@ cgen_doc_header_and_toc();
emit(e);
emit(o);
emit(i);
emit(t);
emit(a);
emit(t);
emit('</BODY>');
emit('</HTML>');
cgen_write_current_snippet();
......@@ -3049,19 +3081,19 @@ cgen_new_snippet();
emit("\\subsubsection{Register description}");
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_reg(e);end end);
local o=cgen_get_snippet();
local a="";
local t="";
if(periph.ramcount>0)then
emit("\\subsubsection{Memory blocks}");
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_ram(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
local t="";
local a="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit("\\subsubsection{Interrupts}");
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_irq(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_lx_memmap();
......@@ -3070,8 +3102,8 @@ cgen_new_snippet();
cgen_doc_lx_header_and_toc();
emit(e);
emit(o);
emit(a);
emit(t);
emit(a);
cgen_write_current_snippet();
end
function gen_hdl_field_prefix(a,e)
......@@ -3147,163 +3179,163 @@ t.ackgen_code_pre={va(e.."_int",e.."_int_delay");
va(e.."_int_delay",0);};
end
end
function gen_hdl_code_bit(e,a)
local t=gen_hdl_field_prefix(e,a);
e.prefix=t;
if(e.clock==nil)then
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int")};
e.acklen=1;
e.write_code={
va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={va(t.."_o",t.."_int")};
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.reset_code_main={};
e.extra_code={};
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
elseif(e.access==ACC_RW_RW)then
if(e.load==LOAD_EXT)then
e.ports={port(BIT,0,"out",t.."_o","Ports for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.acklen=1;
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.write_code={
va(t.."_load_o",1)};
e.extra_code={va(t.."_o",vi("wrdata_reg",e.offset))};
e.ackgen_code_pre={va(t.."_load_o",0)};
e.ackgen_code={va(t.."_load_o",0)};
e.reset_code_main={va(t.."_load_o",0)};
function gen_hdl_code_bit(t,a)
local e=gen_hdl_field_prefix(t,a);
t.prefix=e;
if(t.clock==nil)then
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int")};
t.acklen=1;
t.write_code={
va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={va(e.."_o",e.."_int")};
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.reset_code_main={};
t.extra_code={};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
elseif(t.access==ACC_RW_RW)then
if(t.load==LOAD_EXT)then
t.ports={port(BIT,0,"out",e.."_o","Ports for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.acklen=1;
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.write_code={
va(e.."_load_o",1)};
t.extra_code={va(e.."_o",vi("wrdata_reg",t.offset))};
t.ackgen_code_pre={va(e.."_load_o",0)};
t.ackgen_code={va(e.."_load_o",0)};
t.reset_code_main={va(e.."_load_o",0)};
else
die("internal RW/RW register storage unsupported yet ("..e.name..")");
die("internal RW/RW register storage unsupported yet ("..t.name..")");
end
end
else
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int"),
signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=4;
e.write_code={va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RW/RO, clk_sys_i <-> "..e.clock..")");
vsyncprocess(e.clock,"rst_n_i",{
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int"),
signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=4;
t.write_code={va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RW/RO, clk_sys_i <-> "..t.clock..")");
vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{
va(t.."_o",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync0",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync1",csel(e.reset_value==nil,0,e.reset_value));
va(e.."_o",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync0",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync1",csel(t.reset_value==nil,0,t.reset_value));
});
vposedge({
va(t.."_sync0",t.."_int");
va(t.."_sync1",t.."_sync0");
va(t.."_o",t.."_sync1");
va(e.."_sync0",e.."_int");
va(e.."_sync1",e.."_sync0");
va(e.."_o",e.."_sync1");
});
});
};
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_sync1")};
e.reset_code_main={};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RO/WO, "..e.clock.." -> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_sync1")};
t.reset_code_main={};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RO/WO, "..t.clock.." -> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{
va(t.."_sync0",0);
va(t.."_sync1",0);
va(e.."_sync0",0);
va(e.."_sync1",0);
});
vposedge({
va(t.."_sync0",t.."_i");
va(t.."_sync1",t.."_sync0");
va(e.."_sync0",e.."_i");
va(e.."_sync1",e.."_sync0");
});
});
};
elseif(e.access==ACC_RW_RW)then
if(e.load~=LOAD_EXT)then
elseif(t.access==ACC_RW_RW)then
if(t.load~=LOAD_EXT)then
die("Only external load is supported for RW/RW bit fields");
end
local a="Ports for asynchronous (clock: "..e.clock..") RW/RW BIT field: '"..e.name.."' in reg: '"..a.name.."'";
e.ports={port(BIT,0,"out",t.."_o",a,VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.signals={signal(BIT,0,t.."_int_read"),
signal(BIT,0,t.."_int_write"),
signal(BIT,0,t.."_lw"),
signal(BIT,0,t.."_lw_delay"),
signal(BIT,0,t.."_lw_read_in_progress"),
signal(BIT,0,t.."_lw_s0"),
signal(BIT,0,t.."_lw_s1"),
signal(BIT,0,t.."_lw_s2"),
signal(BIT,0,t.."_rwsel")};
e.acklen=6;
e.write_code={
va(t.."_int_write",vi("wrdata_reg",e.offset));
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",1);};
e.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",e.offset),vundefined());
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",1);
va(t.."_rwsel",0);});};
e.reset_code_main={va(t.."_lw",0);
va(t.."_lw_delay",0);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",0);
va(t.."_int_write",0);
local a="Ports for asynchronous (clock: "..t.clock..") RW/RW BIT field: '"..t.name.."' in reg: '"..a.name.."'";
t.ports={port(BIT,0,"out",e.."_o",a,VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.signals={signal(BIT,0,e.."_int_read"),
signal(BIT,0,e.."_int_write"),
signal(BIT,0,e.."_lw"),
signal(BIT,0,e.."_lw_delay"),
signal(BIT,0,e.."_lw_read_in_progress"),
signal(BIT,0,e.."_lw_s0"),
signal(BIT,0,e.."_lw_s1"),
signal(BIT,0,e.."_lw_s2"),
signal(BIT,0,e.."_rwsel")};
t.acklen=6;
t.write_code={
va(e.."_int_write",vi("wrdata_reg",t.offset));
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",1);};
t.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",t.offset),vundefined());
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",1);
va(e.."_rwsel",0);});};
t.reset_code_main={va(e.."_lw",0);
va(e.."_lw_delay",0);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",0);
va(e.."_int_write",0);
};
e.ackgen_code_pre={va(t.."_lw",t.."_lw_delay");
va(t.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(t.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",e.offset),t.."_int_read");
va(t.."_lw_read_in_progress",0);
t.ackgen_code_pre={va(e.."_lw",e.."_lw_delay");
va(e.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(e.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",t.offset),e.."_int_read");
va(e.."_lw_read_in_progress",0);
});
};
e.extra_code={vcomment("asynchronous BIT register : "..e.name.." (type RW/WO, "..e.clock.." <-> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
t.extra_code={vcomment("asynchronous BIT register : "..t.name.." (type RW/WO, "..t.clock.." <-> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
vreset(0,{
va(t.."_lw_s0",0);
va(t.."_lw_s1",0);
va(t.."_lw_s2",0);
va(t.."_int_read",0);
va(t.."_load_o",0);
va(t.."_o",0);
va(e.."_lw_s0",0);
va(e.."_lw_s1",0);
va(e.."_lw_s2",0);
va(e.."_int_read",0);
va(e.."_load_o",0);
va(e.."_o",0);
});
vposedge({
va(t.."_lw_s0",t.."_lw");
va(t.."_lw_s1",t.."_lw_s0");
va(t.."_lw_s2",t.."_lw_s1");
vif(vand(vequal(t.."_lw_s2",0),vequal(t.."_lw_s1",1)),{
vif(vequal(t.."_rwsel",1),{
va(t.."_o",t.."_int_write");
va(t.."_load_o",1);
va(e.."_lw_s0",e.."_lw");
va(e.."_lw_s1",e.."_lw_s0");
va(e.."_lw_s2",e.."_lw_s1");
vif(vand(vequal(e.."_lw_s2",0),vequal(e.."_lw_s1",1)),{
vif(vequal(e.."_rwsel",1),{
va(e.."_o",e.."_int_write");
va(e.."_load_o",1);
},{
va(t.."_load_o",0);
va(t.."_int_read",t.."_i");
va(e.."_load_o",0);
va(e.."_int_read",e.."_i");
});
},{
va(t.."_load_o",0);
va(e.."_load_o",0);
});
});
});
};
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
end
end
end
......@@ -3563,27 +3595,27 @@ e.ports={};
e.acklen=1;
e.read_code={va(vir("rddata_reg",e),e.value);};
end
function fill_unused_bits(i,e)
function fill_unused_bits(o,e)
local a={};
local t={};
local o=true;
local i=true;
foreach_subfield(e,function(e,t)
if(e.type==SLV or e.type==SIGNED or e.type==UNSIGNED or e.type==CONSTANT)then
for e=e.offset,(e.offset+e.size-1)do a[e]=1;end
elseif(e.type==BIT or e.type==MONOSTABLE)then
a[e.offset]=1;
end
if(e.access_bus~=WRITE_ONLY)then o=false;end
if(e.access_bus~=WRITE_ONLY)then i=false;end
end);
if(o)then
if(i)then
for e=0,DATA_BUS_WIDTH-1 do
table_join(t,{va(vi(i,e),vundefined());});
table_join(t,{va(vi(o,e),vundefined());});
end
return t;
end
for e=0,DATA_BUS_WIDTH-1 do
if(a[e]==nil)then
table_join(t,{va(vi(i,e),vundefined());});
table_join(t,{va(vi(o,e),vundefined());});
end
end
return t;
......@@ -3723,7 +3755,7 @@ signal(BIT,0,"eic_idr_write_int");};
["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local i={["__type"]=TYPE_REG;
local o={["__type"]=TYPE_REG;
["__blockindex"]=1000001;
["align"]=1;
["name"]="Interrupt enable register";
......@@ -3739,7 +3771,7 @@ signal(BIT,0,"eic_ier_write_int");};
["extra_code"]={va(vi("eic_ier_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local o={["__type"]=TYPE_REG;
local i={["__type"]=TYPE_REG;
["__blockindex"]=1000002;
["align"]=1;
["name"]="Interrupt status register";
......@@ -3829,17 +3861,17 @@ if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end
table.insert(s,n);
table.insert(o,t);
table.insert(i,t);
table.insert(a,r);
table.insert(i,h);
table.insert(o,h);
end);
add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int");
});
table.insert(periph,s);
table.insert(periph,i);
table.insert(periph,a);
table.insert(periph,o);
table.insert(periph,a);
table.insert(periph,i);
local e={vgm("g_num_interrupts",periph.irqcount);
vpm("clk_i","clk_sys_i");
vpm("rst_n_i","rst_n_i");
......@@ -4036,11 +4068,11 @@ local s={
["hdl_prefix"]=e.hdl_prefix.."_CSR";
["no_std_regbank"]=true;
};
function gen_fifo_csr_field(a,n,t,r,h,o,d,i)
function gen_fifo_csr_field(d,i,t,r,h,o,a,n)
if(e.flags_bus==nil)then
return;
end
if inset(a,e.flags_bus)then
if inset(d,e.flags_bus)then
local t={
["__type"]=TYPE_FIELD;
["name"]=t;
......@@ -4049,21 +4081,21 @@ local t={
["access_dev"]=WRITE_ONLY;
["type"]=o;
["size"]=h;
["offset"]=d;
["c_prefix"]=n;
["hdl_prefix"]=n;
["offset"]=a;
["c_prefix"]=i;
["hdl_prefix"]=i;
["signals"]={};
["read_code"]={};
["ack_len"]=2;
};
local a=e.full_prefix.."_"..n.."_int";
if(i==nil)then
i=true
local a=e.full_prefix.."_"..i.."_int";
if(n==nil)then
n=true
else
i=false
n=false
end
if(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",a)});
if(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",a)});
end
table_join(t.signals,{signal(csel(o==MONOSTABLE,BIT,o),h,a)});
if(o==BIT)then
......@@ -4079,8 +4111,8 @@ table_join(t.read_code,{va(vi("rddata_reg",t.offset),0)});
t.ackgen_code={va(a,0)}
end
table.insert(s,t);
elseif(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",vopenpin())});
elseif(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",vopenpin())});
end
end
gen_fifo_csr_field(FIFO_FULL,
......@@ -4245,31 +4277,31 @@ gen_pipelined_wb_signals(e);
foreach_reg(ALL_REG_TYPES,function(e)
gen_abstract_code(e);
end);
local i={};
local o={};
local n={};
local i={};
foreach_field(function(e,t)
table_join(i,e.reset_code_main);
table_join(o,e.reset_code_main);
end);
foreach_reg(ALL_REG_TYPES,function(e)
table_join(i,e.reset_code_main);
table_join(o,e.reset_code_main);
end);
foreach_reg({TYPE_REG},function(e)
foreach_subfield(e,function(e,t)
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
table_join(n,e.ackgen_code);
table_join(i,e.ackgen_code_pre);
end);
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
table_join(n,e.ackgen_code);
table_join(i,e.ackgen_code_pre);
end);
local e={};
foreach_reg({TYPE_REG},function(t)
local i=find_max(t,"acklen");
local n=find_max(t,"acklen");
local a={};
local o={};
foreach_subfield(t,function(e,t)table_join(o,e.write_code);end);
foreach_subfield(t,function(e,t)table_join(a,e.read_code);end);
local n=fill_unused_bits("rddata_reg",t);
local i=fill_unused_bits("rddata_reg",t);
table_join(o,t.write_code);
table_join(a,t.read_code);
local a={
......@@ -4277,10 +4309,10 @@ vif(vequal("wb_we_i",1),{
o,
});
a,
n
i
};
if(not(t.dont_emit_ack_code==true))then
table_join(a,{va(vi("ack_sreg",math.max(i-1,0)),1);});
table_join(a,{va(vi("ack_sreg",math.max(n-1,0)),1);});
table_join(a,{va("ack_in_progress",1);});
end
if(regbank_address_bits>0)then
......@@ -4301,13 +4333,13 @@ local t={};
if(periph.fifocount+periph.regcount>0)then
t={vcase(0,e);};
end
foreach_reg({TYPE_RAM},function(e)
local a=csel(options.register_data_output,1,0);
table_join(t,{vcase(e.select_bits,{
foreach_reg({TYPE_RAM},function(a)
local e=csel(options.register_data_output,1,0);
table_join(t,{vcase(a.select_bits,{
vif(vequal("rd_int",1),{
va(vi("ack_sreg",0),1);
},{
va(vi("ack_sreg",a),1);
va(vi("ack_sreg",e),1);
});
va("ack_in_progress",1);
});});
......@@ -4337,14 +4369,14 @@ vreset(0,{
va("ack_sreg",0);
va("ack_in_progress",0);
va("rddata_reg",0);
i
o
});
vposedge({
vcomment("advance the ACK generator shift register");
va(vi("ack_sreg",MAX_ACK_LENGTH-2,0),vi("ack_sreg",MAX_ACK_LENGTH-1,1));
va(vi("ack_sreg",MAX_ACK_LENGTH-1),0);
vif(vequal("ack_in_progress",1),{
vif(vequal(vi("ack_sreg",0),1),{o;va("ack_in_progress",0);},n);
vif(vequal(vi("ack_sreg",0),1),{n;va("ack_in_progress",0);},i);
},{
e
});
......@@ -4353,20 +4385,20 @@ e
};
if(periph.ramcount>0)then
if(not options.register_data_output)then
local t={"rddata_reg","rwaddr_reg"};
local a={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),a);};
local o={vcomment("Data output multiplexer process");vcombprocess(t,o);};
local a={"rddata_reg","rwaddr_reg"};
local t={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),t);};
local o={vcomment("Data output multiplexer process");vcombprocess(a,o);};
foreach_reg({TYPE_RAM},function(e)
table.insert(t,e.full_prefix.."_rddata_int");
local t={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
table.insert(a,e.full_prefix.."_rddata_int");
local a={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
if(e.width<DATA_BUS_WIDTH)then
table_join(t,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
table_join(a,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
end
table_join(a,{vcase(e.select_bits,t);});
table_join(t,{vcase(e.select_bits,a);});
end);
table.insert(t,"wb_adr_i");
table_join(a,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table.insert(a,"wb_adr_i");
table_join(t,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table_join(e,o);
end
local a={"wb_adr_i","rd_int","wr_int"};
......@@ -4414,7 +4446,7 @@ va("wb_ack_o",vi("ack_sreg",0));
});
return e;
end
wbgen2_version="0.7.0-epics"
wbgen2_version="0.7.1-epics"
options={};
options.reset_type="asynchronous";
options.target_interconnect="wb-classic";
......@@ -4453,7 +4485,7 @@ function usage_complete()
print(e)
print(t)
end
function parse_args(o)
function parse_args(a)
local t={
help="h",
version="v",
......@@ -4469,8 +4501,8 @@ cstyle="s",
hstyle="H"
}
local e
local a
e,a=alt_getopt.get_opts(o,"hvC:D:E:K:l:V:s:f:H:p:",t)
local o
e,o=alt_getopt.get_opts(a,"hvC:D:E:K:l:V:s:f:H:p:",t)
for t,e in pairs(e)do
if t=="h"then
usage_complete()
......@@ -4509,11 +4541,11 @@ end
options.hdl_reg_style=e
end
end
if(o[a]==nil)then
if(a[o]==nil)then
usage()
os.exit(0)
end
input_wb_file=o[a];
input_wb_file=a[o];
end
parse_args(arg);
dofile(input_wb_file);
......
wbgen_main.lua
View file @ b7d4a1aa
......@@ -18,7 +18,7 @@
-- MA 02111-1307, USA.
--
wbgen2_version="0.7.0-epics"
wbgen2_version="0.7.1-epics"
options = {};
options.reset_type = "asynchronous";
......
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