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Wishbone slave generator
Commit 8616b045 authored by twlostow's avatar twlostow
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Fixed EIC generation bug (invalid VHDL when there is only 1 interrupts), added… 

Fixed EIC generation bug (invalid VHDL when there is only 1 interrupts), added support for asynchronous FIFOs

git-svn-id: http://svn.ohwr.org/wishbone-gen@14 4537843c-45c2-4d80-8546-c3283569414f
parent 8003bae5
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Showing with 13 additions and 11 deletions
examples/interrupts/run.do
View file @ 8616b045
......@@ -26,7 +26,7 @@ puts $target_filename
../../wbgen2 $input_wb_file -vo $target_filename -consto ./output/vlog_constants.v -co ./output/regdefs.h -lang $lang $wbgen_opt
../../wbgen2 -V $target_filename -K ./output/vlog_constants.v -C ./output/regdefs.h -l $lang $input_wb_file
if { $lang == "verilog" } {
vlog -work work -work wbgen2 $target_filename
......
wbgen_common.lua
View file @ 8616b045
......@@ -80,7 +80,7 @@ function irq(x) x['__type']=TYPE_IRQ; return x; end
function dbg(...)
if(VERBOSE_DEBUG) then print(arg); end
if(VERBOSE_DEBUG ~= 0) then print(arg); end
end
-- function chceks if argument p is nil and if it is, throws fatal error message s
......
wbgen_eic.lua
View file @ 8616b045
......@@ -43,7 +43,7 @@ function wbgen_generate_eic()
["ackgen_code"] = { va("eic_idr_write_int", 0); };
["reset_code_main"] = { va("eic_idr_write_int", 0); };
["acklen"] = 1;
["extra_code"] = { va("eic_idr_int", vi("wrdata_reg", periph.irqcount-1, 0)); };
["extra_code"] = { va(vi("eic_idr_int", periph.irqcount-1, 0), vi("wrdata_reg", periph.irqcount-1, 0)); };
["no_std_regbank"] = true;
};
......@@ -62,7 +62,7 @@ function wbgen_generate_eic()
["ackgen_code"] = { va("eic_ier_write_int", 0); };
["reset_code_main"] = { va("eic_ier_write_int", 0); };
["acklen"] = 1;
["extra_code"] = { va("eic_ier_int", vi("wrdata_reg", periph.irqcount-1, 0)); };
["extra_code"] = { va(vi("eic_ier_int", periph.irqcount-1, 0), vi("wrdata_reg", periph.irqcount-1, 0)); };
["no_std_regbank"] = true;
};
......@@ -78,12 +78,12 @@ function wbgen_generate_eic()
signal (BIT, 0, "eic_isr_write_int"); };
["write_code"] = { va("eic_isr_write_int", 1); };
["read_code"] = { va(vi("rddata_reg", periph.irqcount-1, 0), "eic_isr_status_int"); };
["read_code"] = { va(vi("rddata_reg", periph.irqcount-1, 0), vi("eic_isr_status_int", periph.irqcount-1, 0)); };
["ackgen_code"] = { va("eic_isr_write_int", 0); };
["reset_code_main"] = { va("eic_isr_write_int", 0); };
["acklen"] = 1;
["extra_code"] = { va("eic_isr_clear_int", vi("wrdata_reg", periph.irqcount-1, 0)); };
["extra_code"] = { va(vi("eic_isr_clear_int", periph.irqcount-1, 0), vi("wrdata_reg", periph.irqcount-1, 0)); };
["no_std_regbank"] = true;
};
......@@ -96,7 +96,7 @@ function wbgen_generate_eic()
["hdl_prefix"] = "EIC_IMR";
["signals"] = { signal (SLV, periph.irqcount, "eic_imr_int"); };
["read_code"] = { va(vi("rddata_reg", periph.irqcount-1, 0), "eic_imr_int"); };
["read_code"] = { va(vi("rddata_reg", periph.irqcount-1, 0), vi("eic_imr_int", periph.irqcount-1, 0)); };
["acklen"] = 1;
["no_std_regbank"] = true;
......
wbgen_fifos.lua
View file @ 8616b045
......@@ -335,15 +335,17 @@ function gen_code_fifo(fifo)
if(fifo.clock == nil) then
if(fifo.clock == nil) then -- sync FIFO, single clock
table_join(fifo.maps, { vpm ("clk_i", "bus_clock_int"); });
elseif (fifo.directrion == BUS_TO_CORE) then
else -- async FIFO, dual clocks
if (fifo.direction == BUS_TO_CORE) then
table_join(fifo.maps, { vpm ("rd_clk_i", fifo.clock);
vpm ("wr_clk_i", "bus_clock_int") });
elseif (fifo.direction == CORE_TO_BUS) then
elseif (fifo.direction == CORE_TO_BUS) then
table_join(fifo.maps, { vpm ("wr_clk_i", fifo.clock);
vpm ("rd_clk_i", "bus_clock_int") });
end
end
......@@ -363,7 +365,7 @@ function gen_code_fifo(fifo)
table_join(fifo.extra_code, {
vinstance(fifo.full_prefix.."_INST", "wbgen2_fifo_sync", fifo.maps);
vinstance(fifo.full_prefix.."_INST", csel(fifo.clock == nil, "wbgen2_fifo_sync", "wbgen2_fifo_async"), fifo.maps);
});
......
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