White Rabbit Node Reference Design
The White Rabbit PTP Core (WRPC) is an HDL module that could be easily synthesized and used as a standalone WR interface inside a single FPGA chip or as an IP core in a larger design. WRPC was created to simplify the integration of WR into both existing and embedded devices and systems. This wiki page briefly describes the requirements to Upgrade an existing system and has links to some ""compact standalone solutions"":WRReferenceDesign#Compact-standalone-solutions, which are standalone White Rabbit Node implementations.
WRPC implements an IEEE1588 ordinary clock capable of reaching sub-nanosecond accuracies and working both in Master and Slave modes. In master mode the WRPC uses externally-provided reference time and frequency to synchronize other WR compliant devices. When running in the slave mode, WRPC receives the timing information from a White Rabbit Master, synchronizes its internal clock and provides the timing information for other IP cores through a simple VHDL interface.
The drawing below depicts the internal modules of WRPC:
/1257
Detailed description see:
White Rabbit PTP Core wiki
page
G. Daniluk, White Rabbit PTP Core the sub-nanosecond time
synchronization over Ethernet, MSc Thesis,
Warsaw 2012
G. Daniluk, T. Włostowski, White Rabbit: sub-nanoseconds
synchronization for embedded systems ,
PTTI 2011.
Upgrading an existing system
Only a few additional components are required to upgrade an existing system with the WRPC, presuming the existing project already includes an appropriate FPGA and the required environmental hardware (power supply, configuration etc.). WRPC has been successfully tested with GTP and GTX transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for Altera GX PHYs is currently being implemented.
Block Diagram
The necessary external components are the fiber optic transceiver (SFP
module) and two digitally tunable clock generators (one for the main
PLL, one for producing the DMTD offset frequency).
The use of the remaining components in the block diagram is optional
(supported by WRPC):
- EEPROM (I2C interface), which can store the device's configuration data
- Unique ID / Temperature sensor (one-wire interface), which can be used to build the MAC address
- I/O connector with user I/O signals
The total cost of the external components, including the SFP module is around 75 Euros to which a part of the price of the Xilinx (search price) still should be added.
Operating Power
- FPGA: ~ 1 W
- Clock generators: ~ 700 mW
- FO Transceiver: ~ 500 mW
FPGA Utilization Summary
The table below shows the FPGA utilization summary of the WRPC relevant resources only (WRPC v2.1, Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):
More information:
- Schematic diagram - PDF
file:
https://www.ohwr.org/project/white-rabbit/uploads/8add23567c3dff7030126d7568e08a41/WRPC_upgrade_existing_schematic.pdf
- Altium (summer '09) project
file:
https://www.ohwr.org/project/white-rabbit/uploads/9673e4f6f6013af77591200321a9fbe3/WRPC_upgrade_existing_altium.zip
Compact standalone solutions
Some projects which are standalone White Rabbit Node implementations:
Contacts
- Daniel Florin - Physik Institut, Universitaet Zuerich
- Achim Vollhardt - Physik Institut, Universitaet Zuerich
Useful references
- White Rabbit
- Simple PCIe FMC carrier (SPEC)
- Compliant SFP types
- Building WR PTP Core
- White Rabbit Core Collection
- White Rabbit Software for PTP Core
Daniel Florin - 26 November 2012
Last update: 19 August 2014