Rather than a detailed planning page, this is a list of things to do. Feel free to put your name next to an item if you're working on it, or add new items to the list:
* Pedro is working on spectral quality, stability, etc. i.e. oscillator characterisation theory in general, and he will use that material in the study of PLLs to find the best parameters for them. This will be complemented by real design and measurement.
* César has taken on the subject of very robust FEC codes. This is also clearly !PhD material and does not collide with Pedro's !PhD at all.
* How to implement zero-traffic PTP and still stay PTP-compliant, both in HW and SW.
* When I say "WR's timing performance is equivalent to PTP with a cycle time of 8 ns" I think there is a potential study there: model PTP as a discrete PLL and see the effect of cycle time on accuracy. Then see what happens when you hit the 8 ns limit. Simulations with many cascaded switches should show we have nothing to worry about.
* If somebody found a very clever way for calibrating automatically the non-symmetric delays (i.e. those out of the two-way fiber path) it would be a very very cool thing.
* Right now we are doing a first order split between the two wavelengths, i.e. we just say that if the two way trip took x us, then y% corresponds to one way and z% to the other. This assumes the ratio of propagation speeds is constant with temperature. Maybe potential for some cool stuff here as well, more on the Physics side.
* How to implement a switch efficiently inside an FPGA? The brute force approach is an nXn matrix, i.e. any one of the n ports can talk to any other port through a dedicated path, no sharing, no collisions, but lots of silicon expenditure. Can we be a bit more clever? This question will need to be answered quite soon: we need to design the MCH FPGA.
* Distributed DDS. See this thread in the mailing list. Can we find a generic way of transmitting an arbitrary RF frequency over WR?
* Pedro is also working on modelling the DMTD and see things like the impact of the "offset clock" stability on phase measurement precision.
* RDMA or similar. We have not yet tackled the problem of what to put on top of WR to get a working system for a given need. One of the needs we're already aware of is Ethernet-based memory mapping, i.e. a way for an Ethernet frame to produce a read or write operation in the device which receives it. Thinking of a possible implementation is a matter of minutes, e.g. devote some bits in the frame for the address, a bit for R/W select, another field for data, etc. But there are surely standards out there. Super-computing seems to be a field where this need is commonplace, and some solutions exist: RDMA, Intel's Direct Ethernet Transport (DET), etc. We need it to be implemented easily in an FPGA, and with no retries or other artifacts that can interfere with precise time of delivery. Something on top of UDP is acceptable, but not on top of TCP.
-- Main.JavierSerrano - 23 Nov 2009