V3.0-V3.2: switching DDMTD clock frequency
The DDMTD clock frequency is currently fixed at 62.5 MHz, causing routing problems for firmwares with > 8 ports (ISE is unable to use a global clock network, because there are too many non-clock loads on the signal). In order to fix this, one should distribute a 125 MHz DDMTD clock divided by 2 (single FF) just before sampling (in "reversed" mode
- i.e. DDMTD clock sampled by the measured clock). I recommend enabling the FPGA to select between 62.5 and 125 MHz DDMTD clock.
In the already-produced PCBs, the fix can be done by:
- removing R62,
- cutting the +3V0_VM53_EN trace (the signal is not used in the WRS
design) on the bottom layer right next to a via between 'MidLayer2' and
'Bottom layer' (near RP5),
- wiring pin AN15 of the FPGA to pin 14 of IC13 (from the nearby via, ~4mm of wire).