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Commit fb415263 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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docs/specs/HDL/WRS_HDL-SW_IF: use common figures

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documents/specifications/HDL/WRS_HDL-SW_IF/Makefile 0 → 100644
View file @ fb415263
all : switch_hdl.pdf
.PHONY : all clean
switch_hdl.pdf : switch_hdl.tex
latex $^
latex $^
dvips switch_hdl
ps2pdf switch_hdl.ps
clean :
rm -f *.eps *.pdf *.dat *.log *.out *.aux *.dvi *.ps *.toc
documents/specifications/HDL/WRS_HDL-SW_IF/doc/Makefile 0 → 100644
View file @ fb415263
all:
wbgen2 -f latex -D wrsw_endpoint.tex wbgen/ep_wishbone_controller.wb
wbgen2 -f latex -D i2c_master.tex wbgen/i2c_master.wb
wbgen2 -f latex -D wrsw_endpoint_mdio.tex wbgen/pcs_regs.wb
wbgen2 -f latex -D wr_pps_gen.tex wbgen/pps_gen_wb.wb
wbgen2 -f latex -D wb_simple_uart.tex wbgen/simple_uart_wb.wb
wbgen2 -f latex -D wb_gpio.tex wbgen/wb_gpio.wb
wbgen2 -f latex -D wb_vic.tex wbgen/wb_slave_vic.wb
wbgen2 -f latex -D wrsw_nic.tex wbgen/wr_nic.wb
wbgen2 -f latex -D wrsw_pstats.tex wbgen/wrsw_pstats.wb
wbgen2 -f latex -D wrsw_rtu.tex wbgen/wrsw_rtu.wb
wbgen2 -f latex -D wrsw_txtsu.tex wbgen/wrsw_txtsu.wb
wbgen2 -f latex -D wrsw_tru.tex wbgen/tru_wishbone_slave.wb
wbgen2 -f latex -D wrsw_tatsu.tex wbgen/tatsu_wishbone_controller.wb
wbgen2 -f latex -D wb_simple_pwm.tex wbgen/simple_pwm_wb.wb
wbgen2 -f latex -D wrsw_hwiu.tex wbgen/wrsw_hwiu.wb
documents/specifications/HDL/WRS_HDL-SW_IF/doc/i2c_master.tex 0 → 100644
View file @ fb415263
This diff is collapsed.
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wb_gpio.tex 0 → 100644
View file @ fb415263
\subsection{Wishbone GPIO}
\label{subsec:wbgen:gpio}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & Clear Output Register & gpio\_codr & CODR\\
0x4& REG & Set Output Register & gpio\_sodr & SODR\\
0x8& REG & Data Direction Register & gpio\_ddr & DDR\\
0xc& REG & Pin State Register & gpio\_psr & PSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Clear Output Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_codr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & CODR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CODR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CODR
} [\emph{write-only}]: Clear GPIO outputs
\\
Each bit corresponds to one GPIO line \\ write 1 to bit n: clear n-th line \\ write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Set Output Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_sodr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & SODR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SODR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
SODR
} [\emph{write-only}]: Set GPIO outputs
\\
Each bit corresponds to one GPIO line \\ write 1 to bit n: set n-th line to 1\\ write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Data Direction Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_ddr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & DDR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DDR
} [\emph{read/write}]: GPIO direction
\\
Each bit corresponds to one GPIO line \\ 1: n-th line is output \\ 0: n-th line is input
\end{small}
\end{itemize}
\paragraph*{Pin State Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & gpio\_psr\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & PSR\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{12pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}PSR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
PSR
} [\emph{read-only}]: Read GPIO inputs
\\
Each bit corresponds to one GPIO line \\ read: current status of n-th input
\end{small}
\end{itemize}
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wb_simple_uart.tex 0 → 100644
View file @ fb415263
\subsection{Simple Wishbone UART}
\label{subsec:wbgen:uart}
A simple Wishbone UART (8N1 mode) with programmable baud rate.
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & Status Register & uart\_sr & SR\\
0x4& REG & Baudrate control register & uart\_bcr & BCR\\
0x8& REG & Transmit data regsiter & uart\_tdr & TDR\\
0xc& REG & Receive data regsiter & uart\_rdr & RDR\\
0x10& REG & Host VUART Tx register & uart\_host\_tdr & HOST\_TDR\\
0x14& REG & Host VUART Rx register & uart\_host\_rdr & HOST\_RDR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Status Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_sr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & SR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RX\_RDY} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TX\_BUSY}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TX\_BUSY
} [\emph{read-only}]: TX busy
\\
1: UART is busy transmitting a byte\\0: UART is idle and ready to transmit next byte
\end{small}
\item \begin{small}
{\bf
RX\_RDY
} [\emph{read-only}]: RX ready
\\
1: UART received a byte and its in RXD register\\0: no data in RXD register
\end{small}
\end{itemize}
\paragraph*{Baudrate control register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_bcr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & BCR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
Register controlling the UART baudrate
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BCR
} [\emph{write-only}]: Baudrate divider setting
\\
Baudrate setting. The value can be calculated using the following equation:\\ BRATE = ((Baudrate * 8) << 9 + (ClockFreq >> 8)) / (ClockFreq >> 7)
\end{small}
\end{itemize}
\paragraph*{Transmit data regsiter}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_tdr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & TDR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}TX\_DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TX\_DATA
} [\emph{write-only}]: Transmit data
\end{small}
\end{itemize}
\paragraph*{Receive data regsiter}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_rdr\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & RDR\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}RX\_DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RX\_DATA
} [\emph{read-only}]: Received data
\end{small}
\end{itemize}
\paragraph*{Host VUART Tx register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_host\_tdr\\
{\bf HW address:} & 0x4\\
{\bf SW prefix:} & HOST\_TDR\\
{\bf SW offset:} & 0x10\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RDY}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{write-only}]: TX Data
\end{small}
\item \begin{small}
{\bf
RDY
} [\emph{read-only}]: TX Ready
\end{small}
\end{itemize}
\paragraph*{Host VUART Rx register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & uart\_host\_rdr\\
{\bf HW address:} & 0x5\\
{\bf SW prefix:} & HOST\_RDR\\
{\bf SW offset:} & 0x14\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}COUNT[15:15]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}COUNT[14:7]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{7}{|c|}{\cellcolor{RoyalPurple!25}COUNT[6:0]} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RDY}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read-only}]: RX Data
\end{small}
\item \begin{small}
{\bf
RDY
} [\emph{read-only}]: RX Ready
\end{small}
\item \begin{small}
{\bf
COUNT
} [\emph{read-only}]: RX FIFO Count
\end{small}
\end{itemize}
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wb_spi.tex 0 → 100644
View file @ fb415263
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documents/specifications/HDL/WRS_HDL-SW_IF/doc/wb_vic.tex 0 → 100644
View file @ fb415263
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documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/i2c_master.wb 0 → 100644
View file @ fb415263
top = peripheral {
name = "Wishbone I2C Master";
hdl_entity = "i2c_wishbone_slave";
prefix = "i2c";
reg {
name = "Clock prescale register LSB";
prefix = "prer_lsb";
field {
name = "Clock prescale LSB";
description = "Bits 7:0 of 16-bit PRER register";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Clock prescale register MSB";
prefix = "prer_msb";
field {
name = "Clock prescale MSB";
description = "Bits 15:8 of 16-bit PRER register. Register stores the prescale value for SCL clock \
scl_clk = clk_sys / (5* PRER) \
a new value can be stored only when the module is disabled (CTR register)";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Control register";
prefix = "ctr";
field {
name = "reserved";
prefix = "rsv";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Interrupt enable";
prefix = "ien";
description = "Enable interrupt generation \
1: interrupt enabled \
0: interrupt disabled";
size = 1;
align = 6;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Enable module";
prefix = "en";
description = "1: module enabled \
0: module disabled";
size = 1;
align = 7;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
}
};
reg {
name = "Transmit/Receive register";
prefix = "txrx";
field {
name = "value";
description = "write: byte to be transmitted to i2c bus \
read: byte received from i2c bus";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Command/Status register";
prefix = "crsr";
field {
name = "value";
description = " write: \
bit 7: generate (repeat) start condition \
bit 6: generate stop consitoin \
bit 5: read from slave \
bit 4: write to slave \
bit 3: if 0, send ACK; if 1, send NACK \
bit 0: acknowledge interrupt \
read: \
bit 7: if 0, received ACK; if 1, no ACK received \
bit 6: i2c bus busy \
bit 5: i2c bus arbitration lost \
bit 1: transfer in progress \
bit 0: interrupt pending";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Interface select register";
prefix = "ifs";
field {
name = "I2C i/f number";
prefix = "if_num";
description = "select I2C interface: \
0: MiniBackplane 0 \
1: MiniBackplane 1 \
2: Sensors I2C";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "I2C Master busy";
prefix = "busy";
description = "write 1: I2C Master is busy and if_num cannot be changed \
write 0: I2C Master free to use, if_num can be set to desired i/f";
size = 1;
align = 7;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}
};
};
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/pps_gen_wb.wb 0 → 100644
View file @ fb415263
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Switch PPS generator and RTC";
description = "Unit generating PPS signals and acting as a UTC real-time clock";
hdl_entity = "pps_gen_wb";
prefix = "ppsg";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Reset counter";
description = "write 1: resets the counter\
write 0: no effect";
prefix = "CNT_RST";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable counter";
description = "1: PPS counter is enabled";
prefix = "CNT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Adjust offset";
description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
write 0: no effect\
read 0: adjustment operation is done\
read 1: adjustment operation is in progress";
prefix = "CNT_ADJ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "Set time";
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 62.5 MHz refernce clock cycles";
prefix = "PWIDTH";
size = 28;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock= "refclk_i";
};
};
reg {
name = "Nanosecond counter register";
description = "Nanosecond part of current time, expressed as number of 62.5 MHz reference clock cycles";
prefix = "CNTR_NSEC";
field {
name = "Nanosecond counter";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (least-significant part)";
description = "Lower 32 bits of current UTC time";
prefix = "CNTR_UTCLO";
field {
name = "UTC Counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (most-significant part)";
description = "Highest 8 bits of current UTC time";
prefix = "CNTR_UTCHI";
field {
name = "UTC Counter";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "Nanosecond adjustment register";
description = "Adjustment value for nanosecond counter";
prefix = "ADJ_NSEC";
field {
name = "Nanosecond adjustment";
type = PASS_THROUGH;
size = 28;
};
};
reg {
name = "UTC Adjustment register (least-significant part)";
description = "Lower 32 bits of adjustment value for UTC";
prefix = "ADJ_UTCLO";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "UTC Adjustment register (most-significant part)";
description = "Highest 8 bits of adjustment value for UTC";
prefix = "ADJ_UTCHI";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 8;
};
};
reg {
name = "External sync control register";
prefix = "ESCR";
field {
name = "Sync to external PPS input";
description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
write 0: no effect\
read 1: external synchronization done\
read 0: external synchronization in progress";
type = BIT;
prefix = "SYNC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+cycles) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TM_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/simple_pwm_wb.wb 0 → 100644
View file @ fb415263
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Simple PWM controller
-- Project : General Cores Collection
-------------------------------------------------------------------------------
-- File : simple_pwm_wb.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-12-10
-- Last update: 2013-01-09
-------------------------------------------------------------------------------
-- Description: A simple, multichannel PWM controller (register layout)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "Simple Pulse Width Modulation Controller";
description = "A very simple multichannel PWM controller.";
prefix = "spwm";
hdl_entity = "simple_pwm_wb";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Prescaler Ratio";
description = "PWM Base clock prescaler. Divides the system clock to obtain the PWM counter clock. The division ratio is (PRESC + 1).";
type = SLV;
size = 16;
prefix = "PRESC";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Period";
description = "PWM Cycle Period. The real-time period value <code>PERIOD * (PRESC + 1) * t_clk_sys</code>. Acceptable values: 0..65534.";
type = SLV;
size = 16;
prefix = "PERIOD";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Status Register";
prefix = "SR";
field {
name = "Channel count";
description = "Number of channels supported by this particular implementation, from 1 to 8. ";
type = SLV;
size = 4;
prefix = "N_CHANNELS";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
drive_reg_template =
{
reg {
name = "Channel %d Drive Register";
description = "Current PWM duty cycle for channel %d.";
prefix = "DR%d";
field {
name = "Value";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
function generate_dregs(n)
local i;
for i=0,n-1 do
local T=deepcopy(drive_reg_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
end
generate_dregs(8);
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/simple_uart_wb.wb 0 → 100644
View file @ fb415263
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Simple Wishbone UART";
description = "A simple Wishbone UART (8N1 mode) with programmable baud rate. ";
prefix = "uart";
hdl_entity = "simple_uart_wb";
reg {
name = "Status Register";
prefix = "SR";
field {
name = "TX busy";
description = "1: UART is busy transmitting a byte\n0: UART is idle and ready to transmit next byte";
prefix = "TX_BUSY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX ready";
description = "1: UART received a byte and its in RXD register\n0: no data in RXD register";
prefix = "RX_RDY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Baudrate control register";
description = "Register controlling the UART baudrate";
prefix = "BCR";
field {
name = "Baudrate divider setting";
description = "Baudrate setting. The value can be calculated using the following equation:\
BRATE = ((Baudrate * 8) << 9 + (ClockFreq >> 8)) / (ClockFreq >> 7)";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Transmit data regsiter";
prefix = "TDR";
field {
name = "Transmit data";
prefix = "TX_DATA";
size = 8;
type = PASS_THROUGH;
};
};
reg {
name = "Receive data regsiter";
prefix = "RDR";
field {
ack_read = "rdr_rack_o";
name = "Received data";
prefix = "RX_DATA";
size = 8;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Host VUART Tx register";
prefix = "HOST_TDR";
field {
name = "TX Data";
prefix = "DATA";
type = PASS_THROUGH;
size = 8;
};
field {
name = "TX Ready";
prefix = "RDY";
type= BIT;
access_dev= WRITE_ONLY;
access_bus=READ_ONLY;
};
};
reg {
name = "Host VUART Rx register";
prefix = "HOST_RDR";
field {
ack_read = "host_rack_o";
name = "RX Data";
prefix = "DATA";
type = SLV;
size = 8;
access_dev= WRITE_ONLY;
access_bus=READ_ONLY;
};
field {
name = "RX Ready";
prefix = "RDY";
type= BIT;
access_dev= WRITE_ONLY;
access_bus=READ_ONLY;
};
field {
name = "RX FIFO Count";
prefix = "COUNT";
type = SLV;
size = 16;
access_dev= WRITE_ONLY;
access_bus=READ_ONLY;
};
};
};
\ No newline at end of file
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/tatsu_wishbone_controller.wb 0 → 100644
View file @ fb415263
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Wishbone Register Block (slave)
-- Project : White Rabbit Time Aware Traffic Shaper
-------------------------------------------------------------------------------
-- File : tatsu_wishbone_controller.wb
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2013-03-01
-- Last update: 2013-03-01
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "Time Aware Traffic Shaper";
-- description = "TATSU controller";
hdl_entity = "tatsu_wishbone_controller";
prefix = "tatsu";
-- ECR
reg {
name = "TATSU Control Register/Status";
prefix = "TCR";
description = "General TATSU control and status register";
field {
name = "";
prefix = "reserved";
type = MONOSTABLE;
};
-- field {
-- name = "Validate new settings, enable TATSU (if disabled)";
-- description = "1: validates settings and enables TATSU\
-- 0: does nothing";
-- prefix = "VALIDATE";
-- type = MONOSTABLE;
-- };
field {
name = "Stop TATSU";
description = "write 1: disable Time Aware Traffic Shapper\
write 0: no effect";
prefix = "DISABLE";
type = MONOSTABLE;
align = 1;
};
-- field {
-- name = "Drop no-HP at HP";
-- description = "Drop transmitted frame when frame with high priority awaits transmission\
-- 1: Enable feature\
-- 0: Disable feature";
-- prefix = "DROP_ENA";
-- type = BIT;
-- align = 8;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
--
-- };
-- field {
-- name = "Min repeat value";
-- description = "Repeats the minimum repeat value which can be set";
-- prefix = "MIN_RPT";
-- type = SLV;
-- size = 8;
-- align = 8;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
--
-- field {
-- name = "TATSU started";
-- description = "1: TATSU is running with the validated settings (the set time has been already reached, now we repeat)\
-- 0: TATSU is not running (probably waiting for the time";
-- prefix = "STARTED";
-- type = BIT;
-- align = 8;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Delayed start";
-- description = "1: The time indicated with the settings as a start has been missed (time adjustment at this particular time) so the start is attempted repeat_cycles later (if attemt successful, the STARTED bit is set)\
-- 0: Normal start";
-- prefix = "DELAYED";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Settings OK";
-- description = "1: The settings has been validated succesfully\
-- 0: If checked after asserting VALIDATE it indicates that settings where not accepted -- the error bit is probably set and indicaes what went wrokng)";
-- prefix = "STG_OK";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Settings Error";
-- description = "1: Indicates Shapers error - check other error bits for details\
-- 0: Shaper seems to be working OK";
-- prefix = "STG_ERR";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Settings Error: TAI value";
-- description = "1: Error triggered by wrong TAI value (probably you tried to set time in the past)\
-- 0: TAI value OK";
-- prefix = "STG_ERR_TAI";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Settings Error: cycle value";
-- description = "1: Error triggered by wrong cycle value\
-- 0: Cycle value OK";
-- prefix = "STG_ERR_CYC";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Settings Error: repeat value";
-- description = "1: Error triggered by wrong repeat value (too small or too big)\
-- 0: Repeat value OK";
-- prefix = "STG_ERR_RPT";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Internal Time Sync Error";
-- description = "1: Shaper stopped working due to the error with synchronizing internal counter with time soruce (tm_cycle_i), this is because the tm_time_valid_i was too long down)\
-- 0: Time Sync OK";
-- prefix = "STG_ERR_SNC";
-- type = BIT;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
};
---- TSR
-- reg {
-- name = "TATSU Settings Register 0";
-- prefix = "TSR0";
-- description = "TATSU Settings register 0";
--
-- field {
-- name = "Quanta";
-- description = "Window length (time measured in quanta=512 bits time)";
-- prefix = "QNT";
-- type = SLV;
-- size = 16;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Window Priorit Mask";
-- description = "Mask which indicates which priorities (Classe of Service) are allowed within the window\
-- 1 at bit N - indicates that traffic on priority N is allowed during Window\
-- 0 at bit N - indicates that traffic on priority N is blocked during Window";
-- prefix = "prio";
-- type = SLV;
-- size = 8;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Start time (hi_TAI)";
-- description = "Start time: high bits of the TAI value [39:32]";
-- prefix = "hTAI";
-- type = SLV;
-- size = 8;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- };
-- reg {
-- name = "TATSU Settings Register 1";
-- prefix = "TSR1";
-- description = "TATSU Settings register 1";
--
--
-- field {
-- name = "Start time (lo_TAI)";
-- description = "Start timeLow bits of the TAI value [31:0]";
-- prefix = "lTAI";
-- type = SLV;
-- size = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- };
-- reg {
-- name = "TATSU Settings Register 2";
-- prefix = "TSR2";
-- description = "TATSU Settings register 2";
--
--
-- field {
-- name = "Start time (cycles)";
-- description = "Start time: cycles part of time";
-- prefix = "cyc";
-- type = SLV;
-- size = 28;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- };
-- reg {
-- name = "TATSU Settings Register 3";
-- prefix = "TSR3";
-- description = "TATSU Settings register 3";
--
--
-- field {
-- name = "Repeat time (cycle)";
-- description = "Repeat time: defines (in cycles units) how often the window shall be repeated";
-- prefix = "cyc";
-- type = SLV;
-- size = 28;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- };
-- reg {
-- name = "TATSU Settings Register 4";
-- prefix = "TSR4";
-- description = "TATSU Settings register 4";
--
--
-- field {
-- name = "Ports mask";
-- description = "Mask which indicated which ports shall be affected by the shaper";
-- prefix = "ports";
-- type = SLV;
-- size = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- };
};
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/wb_gpio.wb 0 → 100644
View file @ fb415263
top = peripheral {
name = "Wishbone GPIO";
hdl_entity = "gpio_wishbone_slave";
prefix = "gpio";
reg {
name = "Clear Output Register";
description = "";
prefix = "codr";
field {
name = "Clear GPIO outputs";
description = "Each bit corresponds to one GPIO line \
write 1 to bit n: clear n-th line \
write 0: no effect";
size = 32;
type = SLV;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
}
};
reg {
name = "Set Output Register";
description = "";
prefix = "sodr";
field {
name = "Set GPIO outputs";
description = "Each bit corresponds to one GPIO line \
write 1 to bit n: set n-th line to 1\
write 0: no effect";
size = 32;
type = SLV;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
}
};
reg {
name = "Data Direction Register";
description = "";
prefix = "ddr";
field {
name = "GPIO direction";
description = "Each bit corresponds to one GPIO line \
1: n-th line is output \
0: n-th line is input";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}
};
reg {
name = "Pin State Register";
description = "";
prefix = "psr";
field {
name = "Read GPIO inputs";
description = "Each bit corresponds to one GPIO line \
read: current status of n-th input";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
}
};
}
documents/specifications/HDL/WRS_HDL-SW_IF/doc/wbgen/wb_slave_vic.wb 0 → 100644
View file @ fb415263
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Vectored Interrupt Controller (VIC)";
description = "Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.";
prefix = "VIC";
hdl_entity = "wb_slave_vic";
reg {
name = "VIC Control Register";
prefix = "CTL";
field {
name = "VIC Enable";
description = "write 1: enable VIC operation \
write 0: disable VIC operation \
read 1: VIC enabled \
read 0: VIC disabled";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "VIC output polarity";
description = "1: IRQ output is active high \
0: IRQ output is active low";
prefix = "POL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulate Edge sensitive output";
description = "1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum. \
0: Normal IRQ master line behavior";
prefix = "EMU_EDGE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulated Edge pulse timer";
description = "Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.";
prefix = "EMU_LEN";
type = SLV;
size = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Raw Interrupt Status Register";
prefix = "RISR";
field {
name = "Raw interrupt status";
description = "Each bit reflects the current state of corresponding IRQ input line. \
read 1: interrupt line is currently active \
read 0: interrupt line is inactive";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Interrupt Enable Register";
prefix = "IER";
field {
name = "Enable IRQ";
description = "write 1: enables interrupt associated with written bit \
write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Disable Register";
prefix = "IDR";
field {
name = "Disable IRQ";
description = "write 1: enables interrupt associated with written bit \
write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Mask Register";
prefix = "IMR";
field {
name = "IRQ disabled/enabled";
description = "read 1: interrupt associated with read bit is enabled \
read 0: interrupt is disabled";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Vector Address Register";
prefix = "VAR";
field {
name = "Vector Address";
description = "Address of pending interrupt vector, read from Interrupt Vector Table";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Software Interrupt Register";
description = "Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.";
prefix = "SWIR";
field {
name = "SWI interrupt mask";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "End Of Interrupt Acknowledge Register";
prefix = "EOIR";
field {
name = "End of Interrupt";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.";
type = PASS_THROUGH;
size = 32;
};
};
ram {
name = "Interrupt Vector Table";
description = "Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register.";
prefix = "IVT_RAM";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
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top = peripheral {
name = "Wishbone SPI";
hdl_entity = "spi_wishbone_slave";
prefix = "spi";
reg {
name = "TX/RX 0";
description = "";
prefix = "tx_rx_0";
field {
name = "Tx/Rx word 0";
size = 32;
type = SLV;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
}
};
reg {
name = "TX/RX 1";
description = "";
prefix = "tx_rx_1";
field {
name = "Tx/Rx word 1";
size = 32;
type = SLV;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
}
};
reg {
name = "TX/RX 2";
description = "";
prefix = "tx_rx_2";
field {
name = "Tx/Rx word 2";
size = 32;
type = SLV;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
}
};
reg {
name = "TX/RX 3";
description = "";
prefix = "tx_rx_3";
field {
name = "Tx/Rx word 3";
size = 32;
type = SLV;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
}
};
reg {
name = "Control register";
prefix = "ctrl";
field {
name = "Length of SPI transfer";
prefix = "len";
size = 7;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Start SPI transfer";
prefix = "go";
size = 1;
align = 8;
type = MONOSTABLE;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
field {
name = "RX negedge";
description = "write 1: data from Slave received on falling SCLK edge \
write 0: data from Slave received on rising SCLK edge";
prefix = "rx_negedge";
size = 1;
align = 9;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "TX negedge";
description = "write 1: data transmitted on falling SCLK edge \
write 0: data transmitted on rising SCLK edge";
prefix = "tx_negedge";
size = 1;
align = 10;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "LSB first";
description = "write 1: LSB first on the line \
write 0: MSB first on the line";
prefix = "lsb";
size = 1;
align = 11;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Interrupt enable";
description = "write 1: IRQ enabled \
write 0: IRQ disabled";
prefix = "irq";
size = 1;
align = 12;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Automatic Slave select";
prefix = "ass";
size = 1;
align = 13;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}
};
reg {
name = "Divider";
description = "";
prefix = "divider";
field {
name = "Divide factor";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}
};
reg {
name = "Select SPI slave";
description = "";
prefix = "ss";
field {
name = "Select slave";
size = 1;
type = SLV;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
}
};
};
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-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit Hardware Debugging Unit
-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
peripheral {
name = "WR Switch Hardware Info Unit";
description = "The module provides basic info about the gateware version. It can be also used for reading registers inside WR Switch Gateware after connecting them to optional dbg input.";
hdl_entity = "hwiu_wishbone_slave";
prefix = "hwiu";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Address of the register";
description = "Which register (among those connected to HWDU) will be read";
prefix = "ADR";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Read error";
description = "read 1: read error, provided address is out of range \
read 0: read done successfully";
prefix = "RD_ERR";
type = BIT;
align = 30;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Read register value";
description = "write 1: read the content \
write 0: no effect \
read 1: reading in progress \
read 0: reading done, register value available";
prefix = "RD_EN";
type = BIT;
align = 31;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Value of the requested register";
description = "The value of the register under ADR from the Control Register";
prefix = "REG_VAL";
field {
name = "register value";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Choose Chipscope input";
description = "Single chipscope module is connected to a MUX, this register is used to contol the MUX";
prefix = "CHPS_ID";
field {
name = "MUX ID";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_1;
};
};
\ No newline at end of file
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\subsection{Time Aware Traffic Shaper}
\label{subsec:wbgen:tatsu}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & TATSU Control Register/Status & tatsu\_tcr & TCR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{TATSU Control Register/Status}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & tatsu\_tcr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & TCR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
General TATSU control and status register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DISABLE} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RESERVED}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RESERVED
} [\emph{write-only}]:
\end{small}
\item \begin{small}
{\bf
DISABLE
} [\emph{write-only}]: Stop TATSU
\\
write 1: disable Time Aware Traffic Shapper\\ write 0: no effect
\end{small}
\end{itemize}
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\subsection{Topology Resolution Unit (TRU)}
\label{subsec:wbgen:tru}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & TRU Global Control Register & tru\_gcr & GCR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{TRU Global Control Register}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & tru\_gcr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & GCR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
Control register containing global (port-independent) settings of the TRU.
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}G\_ENA}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
G\_ENA
} [\emph{read/write}]: TRU Global Enable
\\
Global TRU enable bit. Overrides all port settings.\\ 0: TRU is disabled, it does not affect the forwarding response \\ 1: TRU is enabled.
\end{small}
\end{itemize}
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\section{Introduction}
This document describes Wishbone configuration registers of the modules inside
the Gateware of the White Rabbit Switch. Each section gives a short description of
the module's role in the Switch design and is followed by a detailed description
of each configuration register available through Wishbone bus.
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