Commit b7e2858f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

BE seminar WR intro: cosmetics

parent 2b60b98f
......@@ -109,25 +109,17 @@
\item<1-> Initiated to renovate CERN's control \& timing
\item<2-> Based on well-established standards
\begin{itemize}\scriptsize
\item <3->Ethernet \textcolor{gray}{(IEEE 802.3)}
\item <3->Bridged Local Area Network \textcolor{gray}{(IEEE 802.1Q)}
\item <4->Precision Time Protocol \textcolor{gray}{(IEEE 1588)}
\item <2->Ethernet \textcolor{gray}{(IEEE 802.3)}
\item <2->Bridged Local Area Network \textcolor{gray}{(IEEE 802.1Q)}
\item <2->Precision Time Protocol \textcolor{gray}{(IEEE 1588)}
\end{itemize}
\item<6->Extends standards to provide
\begin{itemize}\scriptsize
\item \color{blue!90}{\textbf{Sub-ns synchronisation}}
\item \color{red}{Deterministic data transfer}
\end{itemize}
\item<7-> Initial specs: links $\leq$10~km \& $\leq$2000 nodes
% \item<7-> Initial network specification:
% \begin{itemize}\scriptsize
% \item Fiber links length: $\leq$10~km
% \item Number of nodes: $\leq$2000
% \end{itemize}
\item<8-> \textbf{Open Source and commercially available}
% \item<9-> Many users worldwide, inc. metrology labs...
\item<7-> Initial specs: links $\leq$10~km \& $\leq$2000 nodes
\item<8-> \textbf{Open Source and commercially available}
\end{itemize}
\textcolor{white}{dddd dsaf asd fasd fdsa fads f dsa fdsa f dsaf dsa fdsa f dsaf dsaf fds}
......@@ -395,15 +387,12 @@
\column{.01\textwidth}
\column{.98\textwidth}
\vspace{-0.5cm}
\begin{block}{FMC-based Hardware Kit}
\begin{itemize}\small
% \item Carrier boards in PCI-Express, VME, PXIe
\item All carrier cards are equipped with a White Rabbit port
\item All carrier cards instantite WR PTP Core
\item Mezzanines can use the accurate clock signal and timecode
\\ (synchronous sampling clock, trigger time tag, ...)
\end{itemize}
\end{block}
\begin{itemize}\small
\item All carrier cards are equipped with a White Rabbit port
\item All carrier cards instantite WR PTP Core
\item Mezzanines can use the accurate clock signal and timecode
\\ (synchronous sampling clock, trigger time tag, ...)
\end{itemize}
\column{.01\textwidth}
\end{columns}
......
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