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[WIP] updating content of presentations per Enrico's feedback

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presentations/WR_Maciej_EFTS_2019/wr_efts_2019.tex
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...@@ -118,8 +118,9 @@ ...@@ -118,8 +118,9 @@
\item \color{blue!90}{\textbf{Sub-ns synchronization}} \item \color{blue!90}{\textbf{Sub-ns synchronization}}
\item \color{red}{{\textbf{Deterministic data transfer}}} \item \color{red}{{\textbf{Deterministic data transfer}}}
\end{enumerate} \end{enumerate}
\item<7-> Open Source with commercial support \item<7-> Initial specs: links up to 10km, $\approx$1000 nodes
\item<8-> Many users worldwide, inc. metrology labs... \item<8-> Open Source with commercial support
\item<9-> Many users worldwide, inc. metrology labs...
\end{itemize} \end{itemize}
% \textcolor{white}{dddd dsaf asd fasd fdsa fads f dsa fdsa f dsaf dsa fdsa f dsaf dsaf fds} % \textcolor{white}{dddd dsaf asd fasd fdsa fads f dsa fdsa f dsaf dsa fdsa f dsaf dsaf fds}
...@@ -196,7 +197,7 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -196,7 +197,7 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\end{center} \end{center}
\end{columns} \end{columns}
\pause \pause\pause\pause\pause\pause
{\scriptsize Users page: \url{http://www.ohwr.org/projects/white-rabbit/wiki/WRUsers}} {\scriptsize Users page: \url{http://www.ohwr.org/projects/white-rabbit/wiki/WRUsers}}
{\scriptsize Article:\textit{White Rabbit Applications and Enhancements}, M.Lipinski et. al, ISPCS2018} {\scriptsize Article:\textit{White Rabbit Applications and Enhancements}, M.Lipinski et. al, ISPCS2018}
\end{frame} \end{frame}
...@@ -227,21 +228,24 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -227,21 +228,24 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\begin{columns}[c] \begin{columns}[c]
\column{.4\textwidth} \column{.4\textwidth}
\begin{center} \begin{center}
\includegraphics[height=5cm]{protocol/ptp_exchange.pdf} \includegraphics[height=5cm]<1>{protocol/ptp_exchange.pdf}
\includegraphics[height=4cm]<2->{protocol/ptpNetwork.jpg}
\end{center} \end{center}
\column{.75\textwidth} \column{.75\textwidth}
\begin{itemize} \begin{itemize}
\item Frame-based synchronisation protocol. \item Frame-based synchronisation protocol
\item Simple calculations: \item Simple calculations:
\begin{itemize} \begin{itemize}
\item link $delay_{ms}$ $\delta_{ms} = \frac{(t_{4}-t_{1}) - (t_{3}-t_{2})}{2}$ \item link $delay_{ms}$ $\delta_{ms} = \frac{(t_{4}-t_{1}) - (t_{3}-t_{2})}{2}$
\item clock $offset_{ms} = t_{2} - (t_{1} + \delta_{ms})$ \item clock $offset_{ms} = t_{2} - (t_{1} + \delta_{ms})$
\end{itemize} \end{itemize}
\item<2> Disadvantages \item<2-> Hierarchical network
\item<3-> Disadvantages
\begin{itemize} \begin{itemize}
\item assumes symmetry of medium \item devices have free-running oscillators
\item all nodes have free-running oscillators
\item frequency drift compensation vs. message exchange traffic \item frequency drift compensation vs. message exchange traffic
\item assumes symmetry of medium
\item timestamps resolution
\end{itemize} \end{itemize}
\end{itemize} \end{itemize}
\end{columns} \end{columns}
...@@ -257,7 +261,8 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -257,7 +261,8 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
%\end{block} %\end{block}
\vspace{-0.2cm} \vspace{-0.2cm}
\begin{center} \begin{center}
\includegraphics[height=4.5cm]{misc/synce_v3.pdf} \includegraphics[height=4.5cm]<1>{misc/synce_v3.pdf}
\includegraphics[height=4.5cm]<2>{p1588/1588-ha-L1vsPTP-simplified.jpg}
\end{center} \end{center}
\end{frame} \end{frame}
...@@ -266,11 +271,12 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -266,11 +271,12 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\begin{itemize} \begin{itemize}
\item Used for precise phase measurements \item Used for precise phase measurements
\item Implemented in FPGA and SoftPLL \item Implemented in FPGA and SoftPLL
\item 62.5MHz WR clock and N=14 results in 3.814kHz output signals \item 62.5MHz WR clk \& N=14 results in 3.814kHz output clocks
\item Theoretical resolution of 0.977ps
\end{itemize} \end{itemize}
\vspace{-0.2cm} \vspace{-0.2cm}
\begin{center} \begin{center}
\includegraphics[width=\textwidth]{misc/dmtd_2N.pdf} \includegraphics[width=\textwidth]{misc/ddmtd_3.jpg}
\end{center} \end{center}
\end{frame} \end{frame}
...@@ -283,39 +289,27 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -283,39 +289,27 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Link delay model}
\begin{center}
\includegraphics[width=0.9\textwidth]{calibration/link-model.pdf}
\end{center}
\begin{itemize}
\item static hardware delays: $\Delta_{TXM}$, $\Delta_{RXM}$, $\Delta_{TXS}$, $\Delta_{RXS}$
\item semi-static hardware delays: $\epsilon_M$, $\epsilon_S$
\item fiber asymmetry coefficient: $\alpha = \frac{\delta_{MS} - \delta_{SM}}{\delta_{SM}}$
\end{itemize}
\pause
\begin{block}{}
Calibration procedure to find $\Delta_{TXM}$, $\Delta_{RXM}$,
$\Delta_{TXS}$, $\Delta_{RXS}$ and $\alpha$.
\end{block}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Link delay model} \begin{frame}{Link delay model}
\begin{center} \begin{columns}
\includegraphics[width=0.9\textwidth]{calibration/link-model.pdf} \column{.65\textwidth}
\end{center} \footnotesize
\begin{itemize} \begin{itemize}
\item static hardware delays: $\Delta_{TXM}$, $\Delta_{RXM}$, $\Delta_{TXS}$, $\Delta_{RXS}$ \item <1->Previous tricks allow high precision of round trip measurement
\item semi-static hardware delays: $\epsilon_M$, $\epsilon_S$ \item <2->Accurate synchronization requires mitigation of link asymmetries
\item fiber asymmetry coefficient: $\alpha = \frac{\delta_{MS} - \delta_{SM}}{\delta_{SM}}$ \item <3->Sources of asymmetry: FPGA, PCB, SFP electrics/optics, wavelenght (1, chromatic dispertion
\end{itemize} \item <4->Link delay model
\pause \begin{itemize}\scriptsize
\begin{block}{} \item \textbf{Fixed delays:} assumed constant, calibrated/measured
Calibration procedure to find $\Delta_{TXM}$, $\Delta_{RXM}$, \item \textbf{Variable delays:} online evaluation with fiber asymmetry coefficient: $\alpha = \frac{\nu_g(\lambda_s)}{\nu_g(\lambda_s)} -1 = \frac{\delta_{MS} - \delta_{SM}}{\delta_{SM}}$
$\Delta_{TXS}$, $\Delta_{RXS}$ and $\alpha$. \end{itemize}
\end{block} \end{itemize}
\column{.5\textwidth}
\includegraphics[width=1.0\textwidth]{protocol/link-delay-model-detailed.jpg}
\end{columns}
\pause\pause\pause\pause
\scriptsize See: \textit{WR Calibration}, version 1.1, G.Daniluk
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Equipment} \section{Equipment}
...@@ -330,15 +324,15 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -330,15 +324,15 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\begin{frame}[t,fragile]{White Rabbit Switch} \begin{frame}[t,fragile]{White Rabbit Switch}
\begin{center} \begin{center}
\includegraphics[width=\textwidth]{switch/wrSwitch_v3_3.jpg} \includegraphics[width=\textwidth]{switch/wrSwitch_v3_3.jpg}
\begin{itemize} \begin{itemize}\small
\item Central element of WR network \item Central element of WR network
\item 18 port gigabit Ethernet switch with WR features \item 18 port gigabit Ethernet switch with WR features
\item Optical transceivers: up to 10km, single-mode fiber \item Default Optical transceivers: up to 10km, single-mode fiber
\item Fully open, commercially available from 4 companies \item Fully open, commercially available from 4 companies
\end{itemize} \end{itemize}
\end{center} \end{center}
\begin{center} \begin{center}\scriptsize
NOTE: Work started on a new switch with 10 gigabit Ethernet NOTE: Work started on a new switch with 10 gigabit Ethernet
\end{center} \end{center}
\end{frame} \end{frame}
...@@ -381,27 +375,122 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -381,27 +375,122 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\end{center} \end{center}
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{Performance} \section{Performance}
\subsection{} \subsection{}
\begin{frame}{WR time transfer performance: basic test setup} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Hardware asymmetry compensation}
\begin{center}\vspace{-0.3cm}
\includegraphics<1-2>[height=2.3cm]{misc/inaccuracy-sources-fixed-delays.jpg}
\includegraphics<3>[height=2.3cm]{protocol/bitslide.jpg}
\includegraphics<4->[height=2.3cm]{misc/inaccuracy-sources-fixed-delays.jpg}
\end{center}
\begin{columns}[c]
\column{0.81\textwidth}\vspace{-0.5cm}
\begin{itemize}\scriptsize
\item<2-> \textbf{Bitslide} -- measurement uncertainty
\begin{itemize}\scriptsize
\item Measured each time link goes up
\item Value provided by GTX of FPGA
\item Error: $\pm$25ps [2]
\item Remedy: ensure bitslide is zero \\(ongoing work at CERN)
\end{itemize}
\item<5-> \textbf{PCB, FPGA, SFP} -- hardware delay uncertainty
\begin{itemize}\scriptsize
\item Calibration uncertiainty: sdev of 2ps [2]
\item Linear dependency on temp (700ps over $-10..55^oC$):
\begin{itemize}\tiny
\item CuteWR: tx $-8.4ps/K$, rx $13.3ps/K$ [1]
\item Switch: 8ps/K [2]
\item WR-Zen: 4ps/K [2]
\end{itemize}
\item Remedy: active compensation \\(implemented for LHASSO, 50ps over $-10..55^oC$ [1])
% \item SFP delay dependency on input power, error up to 30ps [2]
\end{itemize}
\end{itemize}
\begin{center} \column{0.38\textwidth}
\includegraphics[height=7.0cm]{measurements/meas_setup.pdf} \begin{center}
\end{center} \includegraphics<6>[width=\textwidth]{measurements/fixed-delays-temp-dependency.jpg}
\tiny\pause\pause\pause\pause\pause
Figure Figure source: [1]
\end{center}
\end{columns}
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Medium asymmetry compensation}
\begin{center}\vspace{-0.3cm}
\includegraphics[height=2.3cm]{misc/inaccuracy-sources-variable-delays.jpg}
\end{center}
\begin{columns}[c]
\column{0.7\textwidth}\vspace{-0.5cm}
\begin{itemize}\scriptsize
\item<2-> \textbf{SFP} -- tx wavelength uncertainty
\begin{itemize}\scriptsize
\item<3-> Allowed departure from nominal value \\(10nm at 1490nm, 50nm at 1310nm [2])
\item<4-> Linear dependency on SFP temp:
\begin{itemize}\tiny
\item SFP@1310nm: $0.11 ps/(K \cdot km)$ [1]
\item SFP@1490nm: $-0.51 ps/(K \cdot km)$ [1]
\item SFP@1550nm: $1.7ps/(K \cdot km)$ [2]
\end{itemize}
\end{itemize}
\item<5-> \textbf{Fiber} -- chromatic dispersion variation
\begin{itemize}\scriptsize
\item Linear dependency on fiber temp:
\begin{itemize}\tiny
\item G652.D at 1310/1490: $-0.2 ps/(K\cdot km)$ [1]
\item G652.D at 1310/1490: $-0.12 ps/(K\cdot km)$ [2]
\item G652.D at 1490/1550: $-0.05 ps/(K\cdot km)$ [2]
\end{itemize}
\end{itemize}
\item<6-> Significant for links $>10km$
\item<7-> Remedy: temp-stabilized SFP, closer wavelength \\(CH21\& CH23 @ 1560.61 \& 1558.98 in SKA [1])
\end{itemize}
\column{0.45\textwidth}
\begin{center}\vspace{-0.5cm}
\includegraphics<4>[width=0.6\textwidth]{measurements/sfp-temp-dependence.jpg}
\includegraphics<5-6>[width=\textwidth]{measurements/fiber-temp-dependency.jpg}
\includegraphics<7>[width=\textwidth]{applications/SKA-DWDM.jpg}
% \tiny\pause\pause\pause
% Figure source: [1]
\end{center}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Frequency transfer}
\begin{center}\vspace{-0.3cm}
\includegraphics[height=2.3cm]{misc/inaccuracy-sources-freq-transfer.jpg}\\
\includegraphics[width=.85\textwidth]{switch/wrs_v3_3_clocking.png}
\end{center}
\begin{frame}{WR time transfer performance: test results} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{frame}{Frequency transfer}
\begin{center}\vspace{-0.3cm}
\includegraphics[height=2.3cm]{misc/inaccuracy-sources-freq-transfer.jpg}
\end{center}
\begin{columns}[c]
\column{0.7\textwidth}\vspace{-0.5cm}
\begin{itemize}\scriptsize
\item \textbf{External reference input} -- noise
\item \textbf{FPGA \& DDMTD} -- noise
\item \textbf{VCXO} -- nose
\end{itemize}
\column{0.45\textwidth}
\begin{center}\vspace{-0.5cm}
\end{center}
\end{columns}
\begin{center}
\includegraphics[height=6.0cm]{measurements/meas_results2.pdf}
\end{center}
\begin{center}
\scriptsize Reported in 2011: \textit{"White Rabbit: a PTP application for robust sub-nanosecond synchronization} -- M. Lipinski et al, ISPCS2011
\end{center}
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{} \subsection{}
\begin{frame}{Performance Enhancements} \begin{frame}{Performance Enhancements}
...@@ -436,6 +525,94 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline ...@@ -436,6 +525,94 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\end{frame} \end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{}
\begin{frame}{Performance Enhancements}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% \begin{itemize}\scriptsize
% \item The short-term performance of WR
% time-transfer directly depends on two design choices of the
% WRS: the use of an FPGA-based phase detector and the use
% of FPGA-based Gigabit transceivers.
% \item Other sources of
% uncertainty are the electro-optics and optics components.
% \item The WRS has a complex clock generation and distribution
% scheme that consists of 20 digital phase detectors, two LOs,
% and five PLLs. A simplified diagram of the WR schema is
% depicted in Fig. 4 and described in this section.
% \item The results show that the noise of the DDMTD comprises
% flicker PM noise and white PM noise. The flicker noise is
% dominant below 10 Hz and it is typically due to transistor
% noise related to the process technology [26]. The white noise
% limits the phase noise to -108 dBc/Hz and it can be traced to
% thermal noise, DFF meta-stability window and/or to phase
% noise folding due to aliasing (as DDMTD is a sampled
% system). The effect of the DMTD clock signal phase noise on
% the results is shown for ∆t=16 ns in Fig. 8 (red line). The
% effect of the DMTD clock phase noise is negligible
% \item Fig. 9 shows the Modified Allan Deviation (MDEV)
% calculated from the phase-tags. The limiting factor of the
% DDMTD is the flicker PM noise, which is limiting the
% MDEV at τ =1 s to 4E-13. In order to determine the source
% of the measured phase noise, the experiment in the following
% subsection was performed.
% \item The additive phase noise and stability limits measured in
% Section V.D show a mix of white PM noise and flicker PM
% noise. Notably, the phase noise above the Main PLL
% bandwidth is filtered by WR PLL. The phase noise within the
% Main PLL bandwidth is additively propagated by WR PLL.
% The most limiting factor introduced by DDMTD is the
% flicker PM noise, limiting the MDEV at τ =1 s to 4E-13. In
% particular, the flicker PM noise is still dominant at τ =100 s,
% as shown in Fig. 9. Last, the main contributors to flicker PM
% noise are the IOBUFDS LVDS input clocks buffer and clock
% routing.
% \item The stability at τ =1s, although still dominated by
% flicker PM noise, is better on Kintex-7 (28 nm) and
% Kintex UltraScale (20 nm) than in Virtex-6 (40 nm) in the
% WRS. Probably, the transistors size of IOBUFDS and clock
% routing circuitry are scaled down less than the process
% technology.
% \item The additive phase noise introduced by the transmission
% circuitry and CDR circuitry of GTX is as significant as the
% additive phase noise introduced by DDMTD. Notably, the L1
% RX clock noise exhibits a flicker PM noise having a
% magnitude comparable to that of DDMTD (-100 dBc at 1 Hz
% and stability of 4E-13 at τ=1 s). As a result, the noise
% contributions that affect the short-term stability of the WR
% time-transfer are equally shared between DMDTD and GTX,
% which is confirmed by the experiment in VI.B.
% \item The current
% implementation of the WRS suffers from some additional
% issues related to non-optimal design choices. These issues
% result in a jitter which is one order of magnitude worse than
% the fundamental limits explored in this article. The main
% culprits are the use of a noisy internal MMCM PLL (shown
% in Fig. 4) in the Virtex-6 in Grandmaster mode, and
% instabilities in the Main LO induced by cooling airflow in the
% WRS enclosure (box). The former issue is due to the phase
% noise of the clock synthesized by MMCM PLL, the clock
% signal has high phase noise at a frequency offset around
% 1 MHz [19]. Due to the discrete-time nature of DDMTD and
% of WR PLL, the phase noise is folding back in baseband. The
% latter issue was partially solved in [19] with an increased
% control loop bandwidth (from 30 Hz to 200 Hz) of the Main
% LO.
% \item The phase detector introduces a limitation in short-term
% stability equal to MDEV 4E-13 at τ =1 s (ENBW 50 Hz),
% with a flicker PM behavior from τ =1 s to τ =100 s and more.
% The origin of flicker PM is due to the LVDS input clock
% buffer of the currently used FPGA and its related internal
% clock distribution. Similar results are observed for newer
% FPGAs, where a (slightly reduced) flicker PM is still present.
% Notably, the FPGA-implemented Gigabit Transceiver
% has a noise contribution, in terms of short-term stability,
% almost equal to the contribution of the phase detector.
% The experimental proof of the reachability of t
% \end{itemize}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{} \subsection{}
\begin{frame}{Performance Enhancements} \begin{frame}{Performance Enhancements}
...@@ -570,5 +747,17 @@ PC. ...@@ -570,5 +747,17 @@ PC.
http://www.ohwr.org/projects/white-rabbit/wiki http://www.ohwr.org/projects/white-rabbit/wiki
\end{center} \end{center}
\end{frame} \end{frame}
\begin{frame}{References}
\tiny
\begin{itemize}
\item White Rabbit Project:\\\url{https://www.ohwr.org/project/white-rabbit/wikis}
\item Companies selling WR:\\\url{https://www.ohwr.org/project/white-rabbit/wrcompanies}
\item Users of WR:\\\url{https://www.ohwr.org/project/white-rabbit/WRUsers}
\item White Rabbit Applications and Enhancements, M.Lipinski et. al, ISPCS2018\\\url{https://www.ohwr.org/project/white-rabbit/uploads/7f9e67258850d5c036629a509bf2e124/ISPCS2018-WRApplicatoinsAndEnhancements.pdf}
\item WR Calibration, version 1.1, G.Daniluk\\ \url{www.cern.ch/white-rabbit/documents/WR_Calibration-v1.1-20151109.pdf}
\item \textit{Temperature Effect and Correction Method of White Rabbit Timing Link}; Hongming Li, Guanghua Gong, Weibin Pan, Qiang Du, Jianmin Li
\item \textit{DWDM Stabilized Optics for White Rabbit}, Paul Boven
\end{itemize}
\end{frame}
\end{document} \end{document}
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