| ... | ... | @@ -19,6 +19,84 @@ TV](https://www.ohwr.org/news/42)\! |
|
|
|
A [fiber cleaning course](https://www.ohwr.org/news/44) was recently
|
|
|
|
organized to raise awareness about this important issue.
|
|
|
|
|
|
|
|
### WR Switch firmware activities
|
|
|
|
|
|
|
|
We have released WR Switch firmware v5.0 with many improvements in both
|
|
|
|
software and gateware. Inside you will find an updated Buildroot and
|
|
|
|
Linux kernel, added VLANs configuration to the main dot-config file,
|
|
|
|
improved Syslog messages, added tools for reading and writing SFP
|
|
|
|
EEPROMs and much more. On the HDL side, version v5.0 brings among others
|
|
|
|
a new bandwidth throttling module for the
|
|
|
|
traffic going to the ARM CPU and re-written, more efficient multi-port
|
|
|
|
linked list in the Ethernet switching core. Please check [the official
|
|
|
|
news](https://www.ohwr.org/news/43) message about the release. We are
|
|
|
|
currently in the process of integrating WR switches within the CERN
|
|
|
|
monitoring (SNMP) and configuration (dot-config generation from a
|
|
|
|
central database) infrastructure.
|
|
|
|
We plan soon to prepare a v5.0.1 release with several minor software
|
|
|
|
fixes to v5.0. Please check the
|
|
|
|
[issues](https://www.ohwr.org/project/wr-switch-sw/issues) with a target
|
|
|
|
version v5.0.1 for more details.
|
|
|
|
|
|
|
|
### WR PTP Core activities
|
|
|
|
|
|
|
|
We have released v4.0 of the WR PTP Core. This new release adds among
|
|
|
|
others the SNMP and Syslog for remote monitoring as well as VLAN
|
|
|
|
support. On the HDL side, we have re-written the Mini-NIC module to fix
|
|
|
|
problems with handling high loads of traffic and improved a lot the
|
|
|
|
synthesis time with RAM initialization for Xilinx. We took the
|
|
|
|
opportunity of this new release to reorganize the wr-cores HDL
|
|
|
|
repository to add platform and board support modules as well as a few
|
|
|
|
reference designs for officially supported boards. Please check the
|
|
|
|
release user manual for a detailed description of these new modules and
|
|
|
|
instructions for how to use them in your custom designs. In the coming
|
|
|
|
months we would like to expand the platform, board, reference design
|
|
|
|
modules to cover also Xilinx series 7 FPGAs and work on porting the WR
|
|
|
|
PTP Core to Kintex Ultrascale
|
|
|
|
FPGAs.
|
|
|
|
|
|
|
|
### New manufacturer of the WR Switch hardware and the official Production Test Suite
|
|
|
|
|
|
|
|
Creotech Instruments S.A. is another company that started producing WR
|
|
|
|
Switch hardware last year. We have bought a few devices and successfully
|
|
|
|
evaluated them together with GSI to make sure they are produced from the
|
|
|
|
same design files as switches sold by 7Solutions. Currently, we are
|
|
|
|
working together with INCAA to prepare an official Production Test Suite
|
|
|
|
(PTS) for the WR Switch hardware. This PTS
|
|
|
|
consists of a set of tests that can be used either by the companies
|
|
|
|
during production, to verify that all the hardware components are
|
|
|
|
soldered and working properly, or by users to test the hardware in case
|
|
|
|
of
|
|
|
|
failures.
|
|
|
|
|
|
|
|
### SPEC and SVEC PTS-es expanded to assign official MAC addresses by manufacturers.
|
|
|
|
|
|
|
|
Till now, the Ethernet MAC address of a WR port on SPEC and SVEC cards
|
|
|
|
was generated from the 1-Wire thermometer ID. Last year we updated the
|
|
|
|
Production Test Suites (PTS) for SPEC and SVEC cards to allow
|
|
|
|
manufacturers to assign unique MAC addresses from the official pool. The
|
|
|
|
MAC address is stored in the Flash memory and can be used by the default
|
|
|
|
WR PTP Core firmware. The update to PTS-es was sent to all the companies
|
|
|
|
producing these cards. Please contact your supplier if you're interested
|
|
|
|
in having WR Nodes with official MAC
|
|
|
|
addresses.
|
|
|
|
|
|
|
|
### Proof of concept demo of super low latency triggers distribution in White Rabbit.
|
|
|
|
|
|
|
|
In 2016 we made a proof of concept implementation of super low latency
|
|
|
|
trigger distribution in White Rabbit. We added a module that injects
|
|
|
|
special 8B/10B characters to the Ethernet data stream. These special
|
|
|
|
characters are then detected on the other side and interpreted as
|
|
|
|
triggers. Thanks to the fact that the injection and reception is done in
|
|
|
|
the physical layer, the overall latency of the trigger is the result of
|
|
|
|
only the SerDes, PCB and fiber latencies. This opens new possibilities
|
|
|
|
of using White Rabbit as a trigger distribution network in high energy
|
|
|
|
physics experiments. This is currently a proof of concept implementation
|
|
|
|
and still requires more work to be included in the stable release of the
|
|
|
|
WR Switch and WR PTP Core. If you find this interesting for your
|
|
|
|
application, please let us know and have a look at branch *supertrigger*
|
|
|
|
in the wr-cores HDL repository.
|
|
|
|
|
|
|
|
## Tsinghua University
|
|
|
|
|
|
|
|
We have adapted WR technology for a pre-clinical Positron Emission
|
| ... | ... | |
