Frequently Asked Questions Wishbone Serializer Core
Synthesis
Q: Inside the WB serializer core, the "after" construct is widely used. Is it synthesizable?
A: No, the "after" construct is ignored by the synthesizer. The VHDL
simulators like ModelSim recognize it.
It can be used to add a delay to a signal and make it change after the
clock's rising edge. The waveform will be clearer
but it is better not mixing constructs for simulation and constructs for
synthesis.
h2 Design
Q: Are the reset signals asserted low or high?
A: The rst_i is asserted low. The gt_reset_in_i is asserted high.
1 November 2012