The Wishbone serializer core helps to solve the problem of accessing a
Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
another Spartan 6 in a transparent way. Both FPGAs are connected by two
Xilinx Gb serial links, one in each direction. In order to cope with the
high latency and still maintain a good throughput, Wishbone pipelined
access mode is
Sent VFC to Seven Solutions for testing the core (order).
Core working on VFC at Seven Solutions. Documentation written.
Additional tests at CERN show that no flow control is implemented, loosing data in certain circumstances.
Frequently Asked Questions
Q: Inside the WB serializer core, the "after" construct is widely used.
Is it synthesizable?
No, the "after" construct is ignored by the synthesizer. The VHDL
simulators like ModelSim recognize it.
It can be used to add a delay to a signal and make it change after the
clock's rising edge. The waveform will be clearer
but it is better not mixing constructs for simulation and constructs for
Q: Are the reset signals asserted low or high?
The rst_i is asserted low.
The gt_reset_in_i is asserted high.