Description
The Wishbone serializer core helps to solve the problem of accessing a Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in another Spartan 6 in a transparent way. Both FPGAs are connected by two Xilinx Gb serial links, one in each direction. In order to cope with the high latency and still maintain a good throughput, Wishbone pipelined access mode is used.
Documentation
Status
Date | Event |
01-10-2010 | Project start. |
12-11-2010 | document#36 published |
15-12-2010 | Order for development placed. |
07-01-2011 | Start learning on Xilinx Aurora protocol |
21-01-2011 | Test Aurora protocol using two boards sp605 |
23-02-2011 | First version ready using burst cycles |
16-04-2012 | Sent VFC to Seven Solutions for testing the core (order). |
05-06-2012 | Core working on VFC at Seven Solutions. Documentation written. |
Javier Serrano, Erik van der Bij - 22 June 2012