Frequently Asked Questions Wishbone Serializer Core

Design

Q: I see that the project is "On Hold". What does that mean?

Indeed, the project is "On Hold" as we believe it is not needed more for the projects that our section is responsible for. The design was meant to be used on the VFC FMC carrier, but people writing VHDL for this board have already other solutions. Our section will develop applications instead for the SVEC FMC carrier that does not need any Wishbone communication between two FPGA's.

The Wishbone Serializer core is in a working state, but still has a bug that seems to appear only when the clocks on both sides differ largely in frequency. This is documented in Issue 623.

Q: Are the reset signals asserted low or high?

A: The rst_i is asserted low. The gt_reset_in_i is asserted high.

Synthesis

Q: Inside the WB serializer core, the "after" construct is widely used. Is it synthesizable?

A: No, the "after" construct is ignored by the synthesizer. The VHDL simulators like ModelSim recognize it.
It can be used to add a delay to a signal and make it change after the clock's rising edge. The waveform will be clearer
but it is better not mixing constructs for simulation and constructs for synthesis.

21 December 2012