Wishbone Serializer fails at step Translate.

ISE version: 14.7

svn info

Path: .
URL: http://svn.ohwr.org/wb-serializer-core
Repository Root: http://svn.ohwr.org/wb-serializer-core
Repository UUID: b19da9ea-537e-4f45-aeb9-bf10cde9cf34
Revision: 43
Node Kind: directory
Schedule: normal
Last Changed Author: Rafael
Last Changed Rev: 43
Last Changed Date: 2012-12-18 09:14:57 +0100 (Tue, 18 Dec 2012)

chipscope.cdc has defined signals which are missing.
(channel 0)=s_wb_slv_cyc
(channel 72)=s_wb_mst_stall

They are also marked with red color in ChipScope Pro Core Inserter tool.

Started : "Translate".
Running inserter...
Command Line: inserter -intstyle ise -mode insert -ise_project_dir /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA -proj chipscope.cdc -intstyle ise -dd /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo -uc /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/par/VFC_SFPGA.ucf -sd ../IP_cores/fifo/VFC -p xc6slx150t-fgg676-3 /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga.ngc test_vfc_sfpga_cs.ngc
===========
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/inserter: 73: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/cs_common.sh: XIL_DIRS[0]=/opt/Xilinx/14.7/ISE_DS/ISE/: not found
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/inserter: 74: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/cs_common.sh: count++: not found

INFO: [CS-ENV 5] Overriding JRE location with XIL_CS_JRE=/opt/Xilinx/14.7/ISE_DS/ISE/java6/lin64/jre/
Release 14.7 ChipScope Core Inserter 14700.13.286.464
Copyright (c) 1999-2012 Xilinx, Inc. All Rights Reserved.

Command Line: inserter -server -intstyle ise -mode insert -ise_project_dir /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA -proj chipscope.cdc -intstyle ise -dd /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo -uc /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/par/VFC_SFPGA.ucf -sd ../IP_cores/fifo/VFC -p xc6slx150t-fgg676-3 /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga.ngc test_vfc_sfpga_cs.ngc 

ChipScope: Launching Server /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/InserterServer
Connecting to server output stream
Started ChipScope Core Insertion Operation
ngcbuild -dd /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo -sd ../IP_cores/fifo/VFC -p xc6slx150t-fgg676-3 -i /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga.ngc /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga_cs.ngc
    Release 14.7 - ngcbuild P.20131013 (lin64)
    Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

    Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -dd
    /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo -sd
    ../IP_cores/fifo/VFC -p xc6slx150t-fgg676-3 -i
    /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga.ngc
    /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga_cs.n
    gc

    Prepending components to an absolute path is invalid.
    Reading NGO file
    "/home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga.ngc
    " ...
    Loading design module "../IP_cores/fifo/VFC/fifo_async.ngc"...

    Partition Implementation Status
    -------------------------------

      No Partitions were found in this design.

    -------------------------------

    NGCBUILD Design Results Summary:
      Number of errors:     0
      Number of warnings:   0

    Writing NGC file
    "/home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga_cs.
    ngc" ...
    Total REAL time to NGCBUILD completion:  3 sec
    Total CPU time to NGCBUILD completion:   2 sec

    Writing NGCBUILD log file
    "/home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga_cs.
    blc"...

    NGCBUILD done.
Loading CDC project /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/chipscope.cdc
Successfully read project /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/chipscope.cdc
copy /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/test_vfc_sfpga_cs.ngc => /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo/test_vfc_sfpga_cs_signalbrowser.ngo
Generating cores using CORE Generator.  Please be patient as this can take several minutes...
     Using existing cached core /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo/cs_icon_pro/generate_icon_pro.xco
     Using existing cached core /home/cscotg/ohwr/wb-serializer-core/trunk/HDL/ise_VFC_SFPGA/_ngo/cs_ila_pro_0/generate_ila_pro_0.xco
UNIT0: Invalid Signal Detected: DATA (channel 0)=s_wb_slv_cyc
UNIT0: Invalid Signal Detected: DATA (channel 72)=s_wb_mst_stall
ERROR:ChipScope: One or more invalid signal connections detected.
ERROR:ChipScope: Double-click the chipscope.cdc icon in the sources window to edit and fix the CDC project.