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VME64x core

Faq

Last edited by Erik van der Bij
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Frequently Asked Questions

General

Q: what is really the state of the design?

State in March 2013: The VME core has been tested in several configurations, including on several different boards (VFC and SVEC) together in the same crate and with several other modules sending traffic at the same time. Basically to test this core we used our experience that we had built up when testing commercial VME boards. This also used DMA from the processor board used in the crate.

The code has been developed by a company and then CERN had a student who worked for a year on it. We still would like to do a serious review of the code to make sure there are no hidden bugs and just to make it all a bit cleaner.
It is a product that we will support as we will base all our SVEC designs on it. For example the ADC100M mezzanine that you sell will also be ported to the SVEC and will use the core.
Recently we found some errors and corrected them in a few days as can be seen in the Repository. This was on Rev.194. From the commit comments in this same repository you can also quite well follow what is being changed.

Resuming, yes it is a perfectly usable core:

  • The black box testing we've done is a proof that it is working pretty fine.
  • CERN's commitment to use it for all SVEC designs assures it will work and will be maintained in case we find any further bugs.

We will also be happy to receive feedback from you when you'll dig into the code.

Technical

Q: Does the core support RORA mode (Release on Register Access)?

The core does not support the RORA mode.
Furthermore note that the Interrupter implemented has not a queue.
You can implement a queue in your WB application and output a new interrupt request only after a read operation.
This will be the equivalent of a RORA Interrupter.

Q:In which FPGA is it possible to fit the vme64x core?

We are testing the core in the following FPGA:

  • Spartan 6
    • Device: XC6SLX150T
    • Package: FGG676
    • Speed -3
  • Spartan 6
    • Device: XC6SLX150T
    • Package: FGG900
    • Speed -3

You can also fit the vme64x core in a smaller FPGA like the Spartan 6 XC6SLX9, package: FTG 256.
It depends on your WB application.

Davide Pedretti, 30 November 2012