with --pattern option, the utility checks the data read are correct (the board generate a different pattern according to the address). So this also checks the data aren't corrupted during the transfer.
The first transfer is slower. This is because the memory was just allocated but never touched. So before the first transfer, the kernel has to initialize the pages. If the pages are initialized (using memset) before the first DMA transfer, the transfer rate is similar to the next ones.
There is some variations in the transfer rate.
All these measure were done on cdv28 (ELMA crate) using a MEN A20 master (which uses the TSI148 bridge).
The current vmebridge driver (PCI-VME bridge: V1.7 (Feb, 04 2019)) manually split large transfers in blocks of 2048 byte, and thus create many descriptors. This is not needed as the TSI148 chip also split large transfers, but this slows down transfers because the TSI chip has to fetch a new descriptor every 2048 bytes. The measures were done with a modified driver to improve performances.
The current vmebridge driver doesn't support 2eSST mode. The measures were done with a modified driver.
(June 2020) The changes in the drivers have been merged to the develop branch.
Hints to achieve better performances:
use higher clock rate (this design use a 125Mhz clock)
use pipelined wishbone mode.
The figures could be compared with an MBLT transfer:
(The clock cycles are 8ns, dtack is always 0 as it cannot be read by a SVEC board).
The "setup" cost is quite important: the transfer needs 46*8ns (360ns) between the rise of AS and the first data transfer). Then 8 bytes are transferred every 6 cycles (48ns) which is slightly above 160MB/s.