Skip to content

V
VME64x core

Home

Last edited by Erik van der Bij
Page history
This is an old version of this page. You can view the most recent version or browse the history.

VME64x to Wishbone Core

Project description

The VME64x core implements a VME64 slave on one side and a WishBone master on the other without FIFOs in-between.

The core supports SINGLE, BLT (D32), MBLT (D64), 2eVME and 2eSST transfers in A24, A32 and A64 address modes and D08 (OE), D16, D32, D64 data transfers. The core can be configured via implemented CR/CSR configuration space. A ROACK type IRQ controller with one interrupt input and a programmable interrupt level and Status/ID register is provided.

A WishBone side features a pipelined WB master for SINGLE transfers.

!!