VME64x to Wishbone Core
Project description
The VME64x core implements a VME64 slave on one side and a WishBone master on the other without FIFOs in-between.
The core supports SINGLE, BLT (D32), MBLT (D64), 2eVME and 2eSST transfers in A24, A32 and A64 address modes and D08 (OE), D16, D32, D64 data transfers. The core can be configured via implemented CR/CSR configuration space. A ROACK type IRQ controller with one interrupt input and a programmable interrupt level and Status/ID register is provided.
A WishBone side features a pipelined WB master for SINGLE transfers.
VME64x_BlockDiagram.png
Main features¶
* VME64x slave
o CR/CSR space
o ROACK type IRQ controller with one interrupt input and a programmable
interrupt level and Status/ID register
o Supported VME access modes
+ SINGLE, BLT (D32), MBLT (D64)
+ A24, A32 and A64 address modes and D08 (OE), D16, D32, D64 data
transfers
* WishBone master (user side)
o Pipelined WB master for SINGLE transfers
For more details about the project see vme64x user manual
Project information
Documents
- VME64 ANSI/VITA 1 1994
- VME64 Extensions ANSI/VITA 1.1 1997
- Wishbone System-on-chip (SoC) Interconnection Architecture for Portable IP Cores, Revision B4
- ANSI/VITA 1.5-2003 2eSST
Contacts
General question about project
- Erik van der Bij - CERN
Project Status
| Date | Event |
| 01-04-2010 | Start working on project. |
| 25-05-2010 | First HDL release. |
| 10-02-2011 | First register read/write made with the core on the VFC. |
| 01-02-2012 | New student will work full time on project. |
| 03-05-2012 | Core has been modified to implement CSR space. CSR and single R/W working on VFC V2. |
| 10-05-2012 | Working on BLT, MBLT and 2eSST implementation. |
| 06-06-2012 | Added data swap modes. A64, 2eVME and 2eSST not yet implemented. Independent tester added to team. |
| 30-07-2012 | SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided. |
Davide Pedretti 30 July 2012