VME64x Core specifications
==========================

This core implements a VME64x slave - WB master bridge. It provides a complete
and user extendable CR/CSR space, and forward to a wishbone slave VME
transfers.  On the WB side, the addresses are rebased from 0.

Features
--------

* interrupts: 1 with automasking. Once acknowledge by the handler, interrupts
  are masked for 1ms or until deasserted by the slave. The intent is to
  prevent interrupt bursts and to retrigger interrupts if not handled.
* A disable ADEM (set to 0) results in an unimplemented ADER, to reduce gate
  usage.
* CSR Reset bit is handled as a pulse (will reset on the next write).
  This doesn't follow the standard, but is needed for software compatibility.
* DTACK/BERR are supposed to be released at most 30ns once DS is released.
  The design needs 4 clocks to release them, which means the min frequency
  is supposed to 133Mhz

Changes
-------

* Core is smaller (< 1000 slices)
* No retry
* No endianess convertion
* WB data bus is 32 bit
* Internal component declarations removed.
* Async inputs registered with gc_sync_register.

VME interface
-------------

Supported:
* D08(EO), D16, D32
* Addressing mode: A16, A24, A32
* BLT, MBLT
* D08(O), I(7-1), ROAK interrupts
* (compatible with MEN A25 master board)
* CR/CSR space with extensions from VME64x
* Geographic Address (GA), dynamic configuration (ader).
  (TODO: support noga/usega for svec ?)
* Interrupt

Not supported:
* 2eVME
* 2eSST (no hardware)
* Dynamic size (DFSR, DFS)
* Fixed address (FAF)
* Extra Function Mask (EFM)
* XAM (no 2e)
* A40, A64 (not supported by MEN A25)
* MD32 (multiplexed data cycle, only for A40)
* LCK (bus lock)
* UAT (unaligned accesses)
* RMW cycles (but should work)
* ADO, ADOH (address only cycle)
* D08, D16 for BLT (??)
* RETRY (cf rule 2.91 - incompatibility with WB)

WB interface (datasheet)
------------
*  1. Compliant to Wishbone B4 specifications
*  2. Slave
*  3. Signals name follows the specification
*  4. err_i is forwarded to VME as BERR*
*  5. rty_i is not supported
*  6. no TAGs
*  7. Port size is 32 bit
*  8. Port granularity is 8 bit
*  9. Maximum operand size is 8 bit (TBC)
* 10. Data transfer ordering is BIG ENDIAN
* 11. Sequence of data transfer is defined by the VME side
* 12. No CLK_I signal, clock is provided separately.
* Non pipeline behaviour (but compatible with pipeline).

Generics
--------

The generics define values for many CR registers, and the clock period (needed
to follow the VME timing specifications).  See generic declarations for
details.

Ports
-----

In addition to reset and clock, the ports are used for VME and WB signals,
to connect a user defined CSR or CR memory, interrupts from the WB slave,
VME irq level and vector.  See port declaration for details.

TODO:
-----

* Stick DFSR and XAM to 0
* Put FF in IOB for all VME lines


VITAL-1 rules
-------------
[ Master/D64/A64 means N/A as the rule doesn't concern this core]
2.1a: Master
2.69: Master
2.2: Followed
2.3: Followed, excluded from c_AMCAP_ALLOWED. [no TB]
2.70: D64
2.7: Followed
2.8: Followed
2.9: Followed
2.71: A64
2.10: Master
2.11: Followed
2.72: A64
2.73: A40
2.74: Followed (A32, A24, A16 supported)
2.75: Followed (likewise)
2.76: Followed (D16 and D08(EO) supported)
2.77: Followed (likewise)
2.4: Followed (D32 supported)
2.5: Followed (D16 supported)
2.12a: Master
2.78: Master
2.66: Followed
2.79: Master
2.80: Master
2.6: Followed [no TB]
2.68: Followed [no TB]
2.81: Followed (LOCK not accepted)
2.82: Followed (likewise)
2.83: Master
2.84: Followed (lock)
2.85: Followed (CR/CSR layout)
2.86: Followed
2.87: Followed (D08(O) is the data access supported)
2.93: Master
2.18: Followed (A[] and LWORD lines are registered)
2.19: Master
2.20: Master
2.21: Master
2.22: Master
2.23: Master
2.24: Master
2.25: Followed (DATA lines are all driven for read, MBLT not supported)
2.26: Followed (Likewise)
2.27: Master
2.28: Master
2.29: Master
2.30: Master
2.31: Master
2.32: Master
2.33a: Master
2.34a: Master
2.35: Master
2.36: Master
2.37: Master
2.38: Master
2.39: Master
2.40: Master
2.41: Master
2.42: Master
2.43: Master
2.44a: Master
2.94: Master
2.45: Master
2.46a: Master
2.47a: Master
2.48a: Master
2.49: Master
2.50: Master
2.51: Master
2.52: Master
2.95: Master
2.96: Master
2.53a: Followed (VME_DATA_DIR is set only once DSA goes low)
2.54a: Followed
2.55: Followed (number of states in the main FSM + synch FF)
2.28a: Followed (likewise)
2.56a: Followed
2.57: Followed
2.98: TBC
2.58a: Followed (released at the same time)
2.99: TBC (retry)
2.100: TBC (retry)
2.101: TBC (retry)
2.102: TBC (retry)
2.103: TBC (retry)
2.104: TBC (retry)
2.105: TBC (retry)
2.59: Bus timer
2.60: Bus timer

3.x: Arbitration

4.1: Backplace
4.50: Followed (slave can generate interrupt)
4.2 Followed


Perf
----

A24 SCT DMA 0x3d
Read Rate: 10.270429 MB/sec
Write Rate: 10.765994 MB/sec

A24 BLT DMA
Read  Rate: 8.782308 MB/sec
Write Rate: 9.176580 MB/sec

A24 MBLT DMA
Read  Rate: 15.769639 MB/sec
Write Rate: 17.178069 MB/sec