Programming languages used in this repository

  •   VHDL
    89.0 %
  •   SystemVerilog
    7.04 %
  •   Makefile
    1.96 %
  •   Stata
    0.69 %
  •   Python
    0.52 %
  •   Shell
    0.45 %
  •   Verilog
    0.35 %

Commit statistics for dafbb7932439076a60664c8ddb97bd3c5e6ebc97 Mar 31 - Jan 03

  • Total: 215 commits
  • Average per day: 0.1 commits
  • Authors: 14

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