Programming languages used in this repository
-
VHDL
89.01 %
-
SystemVerilog
7.03 %
-
Makefile
1.95 %
-
Stata
0.69 %
-
Python
0.52 %
-
Shell
0.45 %
-
Verilog
0.35 %
Commit statistics for cbaeea360f7a625a8cac0133ce5bb7001c8ef4ce Mar 31 - Oct 02
- Total: 297 commits
- Average per day: 0.1 commits
- Authors: 15
Commits per day of month
Commits per weekday
Commits per day hour (UTC)