Programming languages used in this repository

  •   VHDL
    88.78 %
  •   SystemVerilog
    7.21 %
  •   Makefile
    2.0 %
  •   Stata
    0.71 %
  •   Python
    0.52 %
  •   Shell
    0.43 %
  •   Verilog
    0.35 %

Commit statistics for b51f2ca6928d784a4f0a290fe6b23a08c64c63cf Mar 31 - Nov 30

  • Total: 372 commits
  • Average per day: 0.1 commits
  • Authors: 16

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