Programming languages used in this repository

  •   VHDL
    89.0 %
  •   SystemVerilog
    7.03 %
  •   Makefile
    1.95 %
  •   Stata
    0.69 %
  •   Python
    0.53 %
  •   Shell
    0.45 %
  •   Verilog
    0.35 %

Commit statistics for 92f0bc34297d41807996f939c71727129c135bfa Mar 31 - Nov 21

  • Total: 188 commits
  • Average per day: 0.2 commits
  • Authors: 9

Commits per day of month

Commits per weekday

Commits per day hour (UTC)