Programming languages used in this repository

  •   VHDL
    89.0 %
  •   SystemVerilog
    7.04 %
  •   Makefile
    1.96 %
  •   Stata
    0.69 %
  •   Python
    0.52 %
  •   Shell
    0.45 %
  •   Verilog
    0.35 %

Commit statistics for 9174e0e748aee7ba20589f6f8f66131ecde06462 Mar 31 - Nov 27

  • Total: 353 commits
  • Average per day: 0.1 commits
  • Authors: 16

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