Programming languages used in this repository
-
VHDL
89.0 %
-
SystemVerilog
7.04 %
-
Makefile
1.96 %
-
Stata
0.69 %
-
Python
0.52 %
-
Shell
0.45 %
-
Verilog
0.35 %
Commit statistics for 7c71c06b59654e8267f4f12b8fa40726dff8ffc5 Mar 31 - Oct 24
- Total: 315 commits
- Average per day: 0.1 commits
- Authors: 15
Commits per day of month
Commits per weekday
Commits per day hour (UTC)