Programming languages used in this repository

  •   VHDL
    89.0 %
  •   SystemVerilog
    7.04 %
  •   Makefile
    1.96 %
  •   Stata
    0.69 %
  •   Python
    0.52 %
  •   Shell
    0.45 %
  •   Verilog
    0.35 %

Commit statistics for 71cecbc4b3855b7da5563001efaab8eee6cc122f Mar 31 - Dec 15

  • Total: 381 commits
  • Average per day: 0.1 commits
  • Authors: 17

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