Programming languages used in this repository

  •   VHDL
    88.95 %
  •   SystemVerilog
    7.1 %
  •   Makefile
    1.97 %
  •   Stata
    0.7 %
  •   Python
    0.51 %
  •   Shell
    0.42 %
  •   Verilog
    0.35 %

Commit statistics for 58d3d6193531d2e827aef05a96c8e55b3b1e0bc0 Mar 31 - Mar 06

  • Total: 384 commits
  • Average per day: 0.1 commits
  • Authors: 17

Commits per day of month

Commits per weekday

Commits per day hour (UTC)