Commits · tom-svec7 · Projects / VME64x core

06 Sep, 2021 4 commits
- rtl: some renaming in bridged mode: master -> SYS(FPGA), slave->APP(FPGA) · 833193f0
  Tomasz Wlostowski authored Sep 06, 2021
  
  833193f0
- rtl: connect and safely drive remaining memory I/F signals · 48db76c6
  Tomasz Wlostowski authored Sep 06, 2021
  
  48db76c6
- platform: fix reset for the IOSERDES · 87a162be
  Tomasz Wlostowski authored Sep 06, 2021
  
  87a162be
- platform: fixed kintex7 serdes data connection · aad74ea2
  Tomasz Wlostowski authored Sep 06, 2021
  
  aad74ea2
02 Oct, 2020 1 commit
- Serial bridge fixes to compile both in ISE and Vivado (component declarations from UNISIM, etc.) · afdf7167
  Tomasz Wlostowski authored Oct 02, 2020
  
  afdf7167
11 Dec, 2019 2 commits
- adding missing files · 9d52c5c1
  Tomasz Wlostowski authored Dec 11, 2019
  
  9d52c5c1
- get the thing to P&R successfully on a Kintex7 · 32b8b233
  Tomasz Wlostowski authored Dec 11, 2019
  
  32b8b233
02 Dec, 2019 3 commits
- added .gitignore · 143da27e
  Tomasz Wlostowski authored Dec 02, 2019
  
  143da27e
- sim/vme64x_bfm: crude MBLT model · 9fbfc587
  Tomasz Wlostowski authored Dec 02, 2019
  
  9fbfc587
- serial bridge: initial working version · 2460adc3
  Tomasz Wlostowski authored Dec 02, 2019
  
  2460adc3
27 Nov, 2019 1 commit
- bridge: reads/writes work, wip · 6f359655
  Tomasz Wlostowski authored Nov 27, 2019
  
  6f359655
26 Nov, 2019 1 commit
- wip · e8b874db
  Tomasz Wlostowski authored Nov 26, 2019
  
  e8b874db
25 Nov, 2019 1 commit
- bridge · 0f5490f0
  Tomasz Wlostowski authored Nov 25, 2019
  
  0f5490f0
02 Apr, 2019 1 commit
- Update general-cores submodule URL for new OHWR · 1204aeca
  Tom Levens authored Apr 02, 2019
  
  1204aeca
29 Nov, 2018 1 commit
- Invert RTY assertion logic to make simulators happier · 78cac871
  Dimitris Lampridis authored Nov 23, 2018
  
  78cac871
26 Oct, 2018 4 commits
- Implement amnesia address if parity is wrong · e0f5eaad
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  e0f5eaad
- Add new generic to component declaration · ae052e76
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  ae052e76
- Cleanup alignment of code · c3d44ce4
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  c3d44ce4
- Fix references to ANSI/VITA standards · 45cb91f4
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  45cb91f4
25 Oct, 2018 3 commits
- Add generic to disable CR/CSR · 44f9345f
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  44f9345f
- Normalise case of generics and ports · a2ee4ac4
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  a2ee4ac4
- Propagate defaults to parameters on vme64x_core · cd83b258
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  cd83b258
17 Aug, 2018 4 commits
- run_all.sh: strenghten. · 0ae24a25
  Tristan Gingold authored Aug 17, 2018
  
  0ae24a25
- vme_bus: wait for ack = 0 between MBLT WB xfer. · fd6dce67
  Tristan Gingold authored Aug 17, 2018
  
  fd6dce67
- MTLB: force stb to 1 after the first WB transaction. · c50928bb
  Tristan Gingold authored Aug 17, 2018
  
  c50928bb
- Wait until wb ack is negated before starting the second MBLT wb transaction. · c1ab84ba
  Tristan Gingold authored Aug 17, 2018
  
  c1ab84ba
21 Mar, 2018 1 commit
- hdl: bump general-cores used for simulations in order to bring in the WB int removal done there · 633d3174
  Dimitris Lampridis authored Mar 21, 2018
  
  633d3174
20 Mar, 2018 1 commit
- hdl: further cleanup of WB INT and default value for int input when not used · 73232ebd
  Dimitris Lampridis authored Mar 20, 2018
  
  73232ebd
09 Mar, 2018 1 commit
- Document inverted VME signal from V1 to V2. · a120e226
  Tristan Gingold authored Mar 09, 2018
  
  a120e226
08 Mar, 2018 1 commit
- Add missing separate interrupt input line to component declaration in vme64x package as well · 258f8f68
  Dimitris Lampridis authored Mar 08, 2018
  
  258f8f68
06 Mar, 2018 1 commit
- Use a separate pin for the interrupt input line. · 58d3d619
  Tristan Gingold authored Mar 06, 2018
  
  58d3d619
15 Dec, 2017 3 commits
- hdl/testbench/Makefile: support slashes in TB_DIRS · 5bd45fd2
  Adam Wujek authored Dec 15, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  5bd45fd2
- hdl/testbench: modify Makefile for this repo · 94a9c788
  Adam Wujek authored Dec 15, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  94a9c788
- hdl/testbench: add Makefiel for CI · 71cecbc4
  Adam Wujek authored Dec 15, 2017
```
Makefile copied from Btrain repo
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  71cecbc4
14 Dec, 2017 2 commits
- Add g_WB_GRANULARITY and removed default value of g_CLOCK_PERIOD. · fa34d06e
  Tristan Gingold authored Dec 14, 2017
  
  fa34d06e
- Fix doc (now as asciidoc). · b7033b1e
  Tristan Gingold authored Dec 14, 2017
  
  b7033b1e
13 Dec, 2017 1 commit
- Review doc, fix typos. · a8ed0135
  Tristan Gingold authored Dec 13, 2017
  
  a8ed0135
06 Dec, 2017 2 commits
- [doc] quick review of the user guide · 458475d5
  Maciej Lipinski authored Dec 06, 2017
  
  458475d5
- Second review. · fa163755
  Tristan Gingold authored Dec 06, 2017
  
  fa163755
05 Dec, 2017 1 commit
- UG: document core frequency for performances. · b683077a
  Tristan Gingold authored Dec 05, 2017
  
  b683077a