Signed-off-by: Tom Levens <tom.levens@cern.ch>

Small bugfix. The IRQ timeout was hardcoded and didn't take into account
different clock periods which could be set with the g_clock generic.
Signed-off-by: Tom Levens <tom.levens@cern.ch>

Signed-off-by: Tom Levens <tom.levens@cern.ch>

Also made the IRQ line level sensitive and applied retry timer. This is a rewrite of the IRQ controller, the whole core
needs to be checked again and possibly rewritten too.

There are two reasons for doing so:
- compatibility with Wishbone and the VIC interrupt controller
- possibility of losing an edge-triggered IRQ and hanging interrupts when
  different cores trigger interrupts very close to each other.
The modified interrupter implements a retry mechanism, that is, if the IRQ line
gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle
is repeated on the VME bus.

fixed several bugs: race condition on address decoding (the CTR interrupt issue), invalid reset handling in CROM init sequence & strange combinatorial loop in VME_IRQ_Controller. More bugs await.

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@194 665b4545-5c6b-4c24-801b-41150b02b44b

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@189 665b4545-5c6b-4c24-801b-41150b02b44b

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@164 665b4545-5c6b-4c24-801b-41150b02b44b

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@154 665b4545-5c6b-4c24-801b-41150b02b44b

RST_i signal removed from VME64xCore_Top, add odd parity control, default configuration: WB Data bus 32 bit, module disabled

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@151 665b4545-5c6b-4c24-801b-41150b02b44b

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@142 665b4545-5c6b-4c24-801b-41150b02b44b