VME64x core:e0f5eaadc5ad774cf5a66c273882b89b4e309f1a commitshttps://ohwr.org/project/vme64x-core/commits/e0f5eaadc5ad774cf5a66c273882b89b4e309f1a2018-10-26T11:27:23Zhttps://ohwr.org/project/vme64x-core/commit/e0f5eaadc5ad774cf5a66c273882b89b4e309f1aImplement amnesia address if parity is wrong2018-10-26T11:27:23ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/ae052e7624b06a9367d6efd7667f517563d75544Add new generic to component declaration2018-10-26T11:14:41ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/c3d44ce486824d295bc9938c4e70eb611d1a4133Cleanup alignment of code2018-10-26T09:35:33ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/45cb91f4f7cbd01421ea222e1540e6d913bb9100Fix references to ANSI/VITA standards2018-10-26T08:39:47ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/44f9345f6995d70a5440f2c5a99c2c3fc4eecdeeAdd generic to disable CR/CSR2018-10-25T23:00:22ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/a2ee4ac44503153b30767970d1ee64cc640880b4Normalise case of generics and ports2018-10-25T23:00:16ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/cd83b258e245575534483964969b7bb999b4a165Propagate defaults to parameters on vme64x_core2018-10-25T23:00:09ZTom Levenstom.levens@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/0ae24a25ae24cc9f9830c502a7881795238b54c2run_all.sh: strenghten.2018-08-17T14:09:26ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/fd6dce676551edad0a438fb739d4c5a3845a0caavme_bus: wait for ack = 0 between MBLT WB xfer.2018-08-17T14:09:02ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c50928bb354cca44a1d0915406bf331be13d4587MTLB: force stb to 1 after the first WB transaction.2018-08-17T12:42:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c1ab84ba7bfb6ed5f44c9da759b0424b64dc741eWait until wb ack is negated before starting the second MBLT wb transaction.2018-08-17T11:48:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/633d31749b104d4ca04c569cf3e30c5a6c9902b5hdl: bump general-cores used for simulations in order to bring in the WB int ...2018-03-21T07:59:26ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/73232ebd0c03bb48b74764816ef1dbb06e3505dbhdl: further cleanup of WB INT and default value for int input when not used2018-03-20T16:45:49ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/a120e2262e1cb23fa611dddb7fa3727b520a125cDocument inverted VME signal from V1 to V2.2018-03-09T13:21:53ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/258f8f68fddf0223d7e377d1c75b8fa109410ca9Add missing separate interrupt input line to component declaration in vme64x ...2018-03-08T10:58:15ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/58d3d6193531d2e827aef05a96c8e55b3b1e0bc0Use a separate pin for the interrupt input line.2018-03-06T16:04:27ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5bd45fd2d21ec274165ef1f78f67a52ee2006127hdl/testbench/Makefile: support slashes in TB_DIRS2017-12-15T16:15:32ZAdam Wujekadam.wujek@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9297"><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch"><img alt="Adam Wujek's avatar" src="https://secure.gravatar.com/avatar/bee62ad02d8f8c7c40900167722fb9d3?s=32&d=identicon" class="avatar s16 avatar-inline" title="Adam Wujek"></a><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch">Adam Wujek</a> <<a href="mailto:adam.wujek@cern.ch" title="adam.wujek@cern.ch">adam.wujek@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/94a9c78838bac0e623571afad2e718fd9b4c89e4hdl/testbench: modify Makefile for this repo2017-12-15T15:33:48ZAdam Wujekadam.wujek@cern.chSigned-off-by: <span data-trailer="Signed-off-by:" data-user="9297"><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch"><img alt="Adam Wujek's avatar" src="https://secure.gravatar.com/avatar/bee62ad02d8f8c7c40900167722fb9d3?s=32&d=identicon" class="avatar s16 avatar-inline" title="Adam Wujek"></a><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch">Adam Wujek</a> <<a href="mailto:adam.wujek@cern.ch" title="adam.wujek@cern.ch">adam.wujek@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/71cecbc4b3855b7da5563001efaab8eee6cc122fhdl/testbench: add Makefiel for CI2017-12-15T14:15:35ZAdam Wujekadam.wujek@cern.ch
Makefile copied from Btrain repo
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9297"><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch"><img alt="Adam Wujek's avatar" src="https://secure.gravatar.com/avatar/bee62ad02d8f8c7c40900167722fb9d3?s=32&d=identicon" class="avatar s16 avatar-inline" title="Adam Wujek"></a><a href="https://ohwr.org/awujek" title="adam.wujek@cern.ch">Adam Wujek</a> <<a href="mailto:adam.wujek@cern.ch" title="adam.wujek@cern.ch">adam.wujek@cern.ch</a>></span>https://ohwr.org/project/vme64x-core/commit/fa34d06e35ca0bfad8eac24aa51713e81639da64Add g_WB_GRANULARITY and removed default value of g_CLOCK_PERIOD.2017-12-14T14:17:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b7033b1e8f48e15a56322f43fe6cf7af2f7540aaFix doc (now as asciidoc).2017-12-14T13:28:28ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a8ed013550646a9d44e876a0af8a9c6ec0109df1Review doc, fix typos.2017-12-13T15:12:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/458475d5d0dcd32c83f20a60f3efb7797341fd6c[doc] quick review of the user guide2017-12-06T16:19:37ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/fa1637550a80cfd3d9aad4a6dc159526d4d3cc58Second review.2017-12-06T16:17:46ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b683077ad20ef252773bec8ac51adbbf0d69e945UG: document core frequency for performances.2017-12-05T10:35:20ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/2865297786a48cd4792a56f7ba23c93339abd2e1Add pdf version of user guide.2017-12-01T09:34:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/67d91596ae416a5b39d84c454dec9c247f678d71Doc update.2017-12-01T09:34:04ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b51f2ca6928d784a4f0a290fe6b23a08c64c63cfRename user guide.2017-11-30T14:46:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/14582d2185d8b42a5ad54ad21e369b0e0127c07fMove user_guide.md2017-11-30T14:45:37ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a1d483d885eabe1d10e1f4ee4b35c89ab57ed6fcClean-up comments.2017-11-30T14:10:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c0affb7f3225aaaabecb994dbf0006083bb93e00Remove g_decoder extractors, simplify a bit the code.2017-11-30T10:59:52ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/cfc5b68e5ec27d6af4065734f92788250eadeef3xvme64x_core: simplify check of invalid bit in decoder.2017-11-30T10:46:02ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/cc95254f0cce4a518e4914629abd74105cf03364Use 2 synchronizers for ds.2017-11-30T10:40:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/2f426d192c261c4b78b72fb511db27bb6f999d22Width of irq_level_i is 3.2017-11-30T10:40:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b98546cabf08e0b151f9e6fa10c8e78f905f47f4WIP: user guide.2017-11-30T10:39:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f682b07a25fdbfd05a754cd647e6453bb715f563User guide: WIP2017-11-30T07:46:12ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b5d758c9caea7c989cdc06b501ae74e3f82c85daReduce a little bit more the number of warnings.2017-11-27T13:05:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/8aaa3368d5de072be25d3e7b51fde0e393f82a16Reduce number of warnings by reducing the length of ader registers.2017-11-27T12:54:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/07c2a3ef87c5f4f532fb41c44d4985e4cad0ff39Remove g_NBR_DECODER.2017-11-27T12:54:13ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/6ce9cc003038eae0a2a219873f8a69cc58fe7d95Update review status (and minor fixes).2017-11-27T12:41:58ZTristan Gingoldtristan.gingold@cern.ch