- 16 Oct, 2020 1 commit
-
-
Tristan Gingold authored
Fix verilog wrapper See merge request !3
-
- 05 Aug, 2020 2 commits
-
-
Tom Levens authored
-
Tom Levens authored
-
- 20 Jul, 2020 4 commits
-
-
Tristan Gingold authored
VME Core 64x wrapper for Verilog instantiation. See merge request !2
-
Mathieu Saccani authored
-
Tristan Gingold authored
Change the generic assignment per index/field in a record type, because it is… See merge request !1
-
Mathieu Saccani authored
Change the generic assignment per index/field in a record type, because it is not compatible with some synthesizers (Synplify for instance).
-
- 04 Jun, 2020 2 commits
-
-
Tristan Gingold authored
Use transfer rate to select number of cycles for setup and hold. Prefetch earlier.
-
Tristan Gingold authored
-
- 24 Apr, 2020 27 commits
-
-
Tristan Gingold authored
In the previous code, a function that is selected but not supported for the AM was masking any following function.
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
And wait until WB transfers are done before accepting a new VME transaction.
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 14 Apr, 2020 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 14 Nov, 2019 1 commit
-
-
Tristan Gingold authored
-
- 11 Nov, 2019 1 commit
-
-
Tristan Gingold authored
-