VME64x core:8593f0498c1788b2773f5eb093b97411925f4b86 commitshttps://ohwr.org/project/vme64x-core/commits/8593f0498c1788b2773f5eb093b97411925f4b862017-11-13T08:47:04Zhttps://ohwr.org/project/vme64x-core/commit/8593f0498c1788b2773f5eb093b97411925f4b86sim: add general-cores as submodule in order to pin it to specific commit2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/6afbfb63ed8cb5298d65e9e023bdd19dd9e152ebsim: ignore files auto-generated by Modelsim2017-11-13T08:47:03ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/c280586a79d3238e3aa0019506ee5a6af9327f06fix minor syntax error in specifications2017-11-06T10:11:34ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/18674fd36ead6b79ff9121fc1a8103c00fcc77f8Remove non-ASCII characters in order to make all sources plain 'ASCII test'2017-11-06T09:02:43ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/f9a19cab0e175eb7a8f3d286f2cff2c9b3a73b18Fix association order (and remove one extra useless generic).2017-10-25T12:14:46ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f210991d50edd758e1bbf1754bb03484e7d81507Add script to run all the test cases.2017-10-25T12:14:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7c71c06b59654e8267f4f12b8fa40726dff8ffc5Implement g_DECODE_AM (for backward compatibility).2017-10-24T09:58:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/10adb5c6514cf72b8b39847edd101b4bbf0d07e3Fix minor style issues.2017-10-19T09:07:24ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/36ef1f9b62f444d78e54ec649e30115dc87f766dMinor spec update.2017-10-19T09:07:04ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/173dd4e49cc7c44eaad3f52711e7e16d55886a0bRemove unused declarations.2017-10-11T12:53:59ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/fbde2002c59e6f80634e35c43ff74302689a0157Fix minor style issues.2017-10-11T07:26:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d3eaf709602ce795da2cd6b58bbc49dd168d2ec5Use gc_sync_register to perform async synchronization.2017-10-11T07:25:26ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e4d8ca3ca3b2030742c0f23a38473f693d91ea8dFix style issues in the testbench.2017-10-09T14:20:38ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d691584f71aff883bee010e6bdc2bc4d868f52d2Remove empty package body.2017-10-09T14:20:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/1820d72ee35bcb9df21c646809b09aa5e7029f66Remove extra vme64x-core directory.2017-10-09T07:02:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5f7e38e7cf07f7e1eae3f3f64884bb5170f7387fFix style.2017-10-09T06:35:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/19318a703fa13c89d6bf058e1739f1273905a4f2Remove trailing spaces, fix max line length.2017-10-05T15:43:55ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4afd68718533d95d56b698b1c12e0ccadff59b81Remove obsolete documents.2017-10-05T08:04:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c8c252f8d5ad628a157bf21b5664232e1f9ec53aFix style (lines too long)2017-10-05T07:05:34ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f98d72780df3d6e46014a570f97854df6e6bf376Fix case.2017-10-04T11:12:44ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f86fd802ee30218fb4a1b6e99ee5305e9cad288ftop_tb: add header, fix generic name.2017-10-02T11:58:53ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0bf32385b04a19a6b8e5ba28b7fa589e5a4fda1dCreate s_vme_addr_dir register to improve timing.2017-10-02T11:45:32ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/88d3fe21ab2e858e34922355d50bb38deed03d53Remove function_o2017-10-02T07:57:14ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/26d4d4532c1ffb31c09ca4d5fd100c998a7e51bcComments.2017-10-02T07:46:10ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/cbaeea360f7a625a8cac0133ce5bb7001c8ef4ceCan configure number of sync registers.2017-10-02T07:13:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/8f3d4b8f5714fe6323e1177179a89af5e323c58aReady to have vme_lword FF in IOBs.2017-10-02T07:00:25ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/18f12bb4a298353fa1e38614c4fffe7a718c49bcPut FF for VME_DATA_i in IOBs, improve MBLT rate2017-10-02T07:00:07ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/948160107cbebb01aba129d6c092c7451346294eAllow VME_ADDR FF to be put in IOBs.2017-09-29T13:52:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/010af55097513711eb1145b5e67da4a4f69d6ea1irq controller: makes use of registers more explicit.2017-09-29T12:10:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/74e4bdd33d4a4de0cfd5f0c200ddaced87ee28deHandle IACK cycles in vme_bus to avoid mux after FF.2017-09-29T09:49:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/8e5d875f7134e0fd6e536a0aa551810d196ce282vme_bus: latch DS and decode address in parallel. Add testcase.2017-09-29T07:10:39ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/affa1990198cc5a3ec33b592a5871f0cb5e10836Add performance numbers in specs.txt2017-09-28T15:31:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d681e2a34577abdf1610001ef6c0661869e2301eDoc improved.2017-09-28T11:33:22ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3d8797da9d728296e05ff06795f309f2b8b83ef6Initial specifications for core v2.2017-09-28T09:55:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c6b3a685fdef4601ef7e1619e304495d666b56ccSupport MBLT.2017-09-27T14:37:01ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4c5c2f7a56fe202b97377af63ac7c27fefa8773bLatch VME_WRITE.2017-09-22T14:09:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/98894891d8c5077b7b2b55620fc88717e6ed5062Remove unused rtl files.2017-09-22T14:09:14ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3a60c1ba9a0539a02cda13c1699a0dde398e8c35Rescind DTACK.2017-09-22T11:37:27ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/95591095dba167818dc19b3d014e91565ad19f54Don't store unused bits of ADER.2017-09-22T11:36:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e068a43f55bb825953f7bdd48745529aa7b35740top_tb: add new scenario2017-09-22T09:50:01ZTristan Gingoldtristan.gingold@cern.ch