VME64x core:3d8797da9d728296e05ff06795f309f2b8b83ef6 commitshttps://ohwr.org/project/vme64x-core/commits/3d8797da9d728296e05ff06795f309f2b8b83ef62017-09-28T09:55:05Zhttps://ohwr.org/project/vme64x-core/commit/3d8797da9d728296e05ff06795f309f2b8b83ef6Initial specifications for core v2.2017-09-28T09:55:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c6b3a685fdef4601ef7e1619e304495d666b56ccSupport MBLT.2017-09-27T14:37:01ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4c5c2f7a56fe202b97377af63ac7c27fefa8773bLatch VME_WRITE.2017-09-22T14:09:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/98894891d8c5077b7b2b55620fc88717e6ed5062Remove unused rtl files.2017-09-22T14:09:14ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3a60c1ba9a0539a02cda13c1699a0dde398e8c35Rescind DTACK.2017-09-22T11:37:27ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/95591095dba167818dc19b3d014e91565ad19f54Don't store unused bits of ADER.2017-09-22T11:36:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e068a43f55bb825953f7bdd48745529aa7b35740top_tb: add new scenario2017-09-22T09:50:01ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/6ed6be9322b3969a01b04077b9883608bed8af33vme_bus: renaming.2017-09-22T09:49:43ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f6f0a7f05459ec0ceb943ced6796e4585d5046c0adjust xvme64x wrapper.2017-09-22T08:54:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0d53219412280b2a37383796ad4de9c7c0619233core: remove support of rty, simplify WB interface.2017-09-22T08:43:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0a8266698a3097eb253ae7874e5e166c3809fc28vme_bus: add comments, simplify berr generation.2017-09-21T14:45:30ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/56ee00aca29ee2871d912fbb2a94350e9bdde89dAdjust AMCAP bits (remove unsupported modes).2017-09-21T12:33:38ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7e121be49014f5be6fd1f06679dc024a929b1189Renaming of signals, remove some intermediate signals.2017-09-21T11:28:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c393707193cee8fcc8626d30d0f700fb60bb1e57Rewrite decoder to decouple it from main FSM.2017-09-20T15:41:35ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/dca5417b8603d9910ad32381ecbf8c2bad564005top_tb: add comments about possible tests.2017-09-20T13:32:09ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/28acc296d580c61806143774ed8e4ba95fcedf60Fix check of supported AM.2017-09-20T13:31:52ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d16833812b73510072bbb0f62ea45b3e6ac7f29fOnly support 32b data WB bus.2017-09-20T13:31:31ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/01b08feed204809c8771496394ab478e7e134613xvme64x_core component: remove unused generics.2017-09-20T09:32:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/16982f5faec3da70a8393d68fbc63666b0889bffvme64x_pack: use common value for WB data and addr size.2017-09-20T09:32:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/9197cf129f7c46f126c694a6bf3da6cd9e80d79ccr_csr: handle the reset bit as a pulse.2017-09-20T09:29:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/40557d7a10fd2c10ed92aaa2acbd189cd4cbae5ccr/csr: remove unimplemented ader to reduce number of registers.2017-09-18T15:23:31ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/ee2fd3ccdfbc17fc760fff89d68d6bce166efb06VME_CR_CSR_Space: add comments.2017-09-18T13:11:42ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/88f59fc3366a97e78016643ea73b575095f0e594Remove reference to A64 in VME_bus.vhd2017-09-18T12:34:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/28197037edebe9ed1344cd8ea514b38d999ad6b4CR_CSR: reduce CR rom size.2017-09-18T12:33:21ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5feb437b7078269e6e0849edce888ff615decf4bUse default values for generics so that CRAM is not enabled.2017-09-18T12:32:31ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e91bc3320b7e1cc6ad85f0f3f4e2f81a153d9518vme64x: simplify again (remove swapper)2017-09-15T15:14:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7a9ed7cf9015209a1d020182b5ed3a1a640d6717Add comment.2017-09-14T08:46:10ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a90f3280df7299817153b35fe418f9b8e14842c3remove DFS, XAM, FAF, EFM. Address width is always 32.2017-09-14T08:42:35ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/abcf3e019f83ddb2750bcad61dacfcb12eaf93a7vme_bus: simplify code, move enumeration type declaration to the arch.2017-09-14T06:41:19ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a80b3d14651cc624570d1eadbce22048a00ac930vme_bus: remove useless signals and disabled code, cleanup2017-09-13T12:46:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e9fe74294a089cf128b031d703674987e79ffcbcvme64xcore: keep function_o width to 4 bits2017-09-13T12:46:04ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/bae9570f3a17d537078d36e6d2e73ec0c6d221bdsimple_tb: add write32 BLT test.2017-09-13T06:52:46ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c6850b1604379ecfce24eed94257f0dacc65f2d0simple_tb: add D32 BLT test2017-09-12T15:32:13ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/fb555fb0c91aec3a63b0a85ac9eebb327ba0efeasimple_tb: add interrupt check2017-09-12T14:45:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/306da800447a3beb61c4a43bf39fd2380ecbf3a9VME_IRQ_Controller: formatting.2017-09-12T14:44:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/03b1ca39945f9d8f96759dce8b8706bdb58a9db3simple_tb: add write322017-09-12T11:33:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/37e459e71b7f31fd36dffd65863b5d60d6a158ccsimple_tb: add write162017-09-12T10:27:26ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/1a75808f270efed8ba6c89dda5e3512464d2d868simple_tb: add write82017-09-12T10:20:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/ad09b2d669282dad1151761cbea4aebbabcdee0esimple_tb: implement read32 and factorize code.2017-09-12T09:14:37ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3ca2a8432ed9cd3b8c342900b322c28b451f1838simple_tb: add read162017-09-12T08:47:25ZTristan Gingoldtristan.gingold@cern.ch