VME64x core:20f51d45431051dfadaee6d3024f92680144e263 commitshttps://ohwr.org/project/vme64x-core/commits/20f51d45431051dfadaee6d3024f92680144e2632017-11-14T09:33:24Zhttps://ohwr.org/project/vme64x-core/commit/20f51d45431051dfadaee6d3024f92680144e263Rename units (to follow file names).2017-11-14T09:33:24ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/af1eb06a73e389d3c94d9ff04c5035af01f47da5Rename file names (to lower case).2017-11-14T09:19:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0508124026d14a3a3b9fbb50bb26fa068e17b8afAdd README, adjust Manifest.py2017-11-14T09:08:56ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/dc69f9301e71563ea61dd9438389a43f8c21b609[submodules] added general-cores as submodules2017-11-14T08:56:30ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/3d3ea084058e1479f5da5a7c7e906f1ba6cd43a2Remove .gitmodules before cherry-pick.2017-11-14T08:56:15ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5be6b4bef82d31ace9112aa5863ab7a109765eaeRestore vme64x_bfm.2017-11-14T08:50:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/78a25d2cfb076f5228094a71256d4ea4d288449eRename sim to testbench2017-11-14T08:47:43ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5cf647bf680df44a239d088cd926542f1c6308e7Remove general-cores.2017-11-14T08:46:47ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/131c5766445760f083992e3a829984bdda5a46e0Update review document after 2017-11-13 review.2017-11-14T08:41:56ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/34239178af11cd512668e457c3eeed5a443c180e[sim] added run.do script to run scenario 1.2017-11-13T13:01:59ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/3ebc1916c69040a1d8bfb618ba60af93dbedd2e7[sim] added wave.do2017-11-13T13:01:42ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/9076173e6fce0827b750be2dbf6107af33351880[desc] small corrections to the description in the VME64xCore_Top.vhd fiel2017-11-13T12:59:19ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/159267795c9d2ee0979fce62e7e0a0698cdfe6ca[desc] small corrections to VME_IRQ_Controller.vhd file2017-11-13T12:59:13ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/f9505f1530d0ccb59aec292e4fde27272d3eee10Greg review update.2017-11-13T12:52:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/250f7da5f73aad9e6cefbb0eaff7ad02b8d32643Remove unused vme64x_bfm.2017-11-13T08:57:49ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7362766427f308585f29d8819c45cc919c363386Add reviews.2017-11-13T08:55:07ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/557e12cf65484a027344339dbd09e543463d1b4dRemove oudated file.2017-11-13T08:52:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/829ccb6f572aa052680b362606277c19d26966a1Rename doc directory.2017-11-13T08:50:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a1bea3a811b2825b8531f269fd479f334693f226use local constants for wishbone address and data width generics of xvme64x_c...2017-11-13T08:47:05ZDimitris LampridisDimitris.Lampridis@cern.chuse local constants for wishbone address and data width generics of xvme64x_core (same as VME64xCore_Top)
https://ohwr.org/project/vme64x-core/commit/e109be6f764a4c5d48d2a72cf1599ae7db83a5ebsim: improve SNR of terminal output2017-11-13T08:47:05ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/3bc0f999558db129b2405b8d4578b9184fed0903sim: no need to invoke modelsim gui at the end of make2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/756ef1a8cca463fda1485e6257c259870971a8acsim: drop "bash-ism" from run_all.sh2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/8593f0498c1788b2773f5eb093b97411925f4b86sim: add general-cores as submodule in order to pin it to specific commit2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/6afbfb63ed8cb5298d65e9e023bdd19dd9e152ebsim: ignore files auto-generated by Modelsim2017-11-13T08:47:03ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/c280586a79d3238e3aa0019506ee5a6af9327f06fix minor syntax error in specifications2017-11-06T10:11:34ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/18674fd36ead6b79ff9121fc1a8103c00fcc77f8Remove non-ASCII characters in order to make all sources plain 'ASCII test'2017-11-06T09:02:43ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/f9a19cab0e175eb7a8f3d286f2cff2c9b3a73b18Fix association order (and remove one extra useless generic).2017-10-25T12:14:46ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f210991d50edd758e1bbf1754bb03484e7d81507Add script to run all the test cases.2017-10-25T12:14:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7c71c06b59654e8267f4f12b8fa40726dff8ffc5Implement g_DECODE_AM (for backward compatibility).2017-10-24T09:58:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/10adb5c6514cf72b8b39847edd101b4bbf0d07e3Fix minor style issues.2017-10-19T09:07:24ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/36ef1f9b62f444d78e54ec649e30115dc87f766dMinor spec update.2017-10-19T09:07:04ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/173dd4e49cc7c44eaad3f52711e7e16d55886a0bRemove unused declarations.2017-10-11T12:53:59ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/fbde2002c59e6f80634e35c43ff74302689a0157Fix minor style issues.2017-10-11T07:26:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d3eaf709602ce795da2cd6b58bbc49dd168d2ec5Use gc_sync_register to perform async synchronization.2017-10-11T07:25:26ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e4d8ca3ca3b2030742c0f23a38473f693d91ea8dFix style issues in the testbench.2017-10-09T14:20:38ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d691584f71aff883bee010e6bdc2bc4d868f52d2Remove empty package body.2017-10-09T14:20:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/1820d72ee35bcb9df21c646809b09aa5e7029f66Remove extra vme64x-core directory.2017-10-09T07:02:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5f7e38e7cf07f7e1eae3f3f64884bb5170f7387fFix style.2017-10-09T06:35:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/19318a703fa13c89d6bf058e1739f1273905a4f2Remove trailing spaces, fix max line length.2017-10-05T15:43:55ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4afd68718533d95d56b698b1c12e0ccadff59b81Remove obsolete documents.2017-10-05T08:04:36ZTristan Gingoldtristan.gingold@cern.ch