VME64x core:1820d72ee35bcb9df21c646809b09aa5e7029f66 commitshttps://ohwr.org/project/vme64x-core/commits/1820d72ee35bcb9df21c646809b09aa5e7029f662017-10-09T07:02:57Zhttps://ohwr.org/project/vme64x-core/commit/1820d72ee35bcb9df21c646809b09aa5e7029f66Remove extra vme64x-core directory.2017-10-09T07:02:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5f7e38e7cf07f7e1eae3f3f64884bb5170f7387fFix style.2017-10-09T06:35:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/19318a703fa13c89d6bf058e1739f1273905a4f2Remove trailing spaces, fix max line length.2017-10-05T15:43:55ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4afd68718533d95d56b698b1c12e0ccadff59b81Remove obsolete documents.2017-10-05T08:04:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c8c252f8d5ad628a157bf21b5664232e1f9ec53aFix style (lines too long)2017-10-05T07:05:34ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f98d72780df3d6e46014a570f97854df6e6bf376Fix case.2017-10-04T11:12:44ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f86fd802ee30218fb4a1b6e99ee5305e9cad288ftop_tb: add header, fix generic name.2017-10-02T11:58:53ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0bf32385b04a19a6b8e5ba28b7fa589e5a4fda1dCreate s_vme_addr_dir register to improve timing.2017-10-02T11:45:32ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/88d3fe21ab2e858e34922355d50bb38deed03d53Remove function_o2017-10-02T07:57:14ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/26d4d4532c1ffb31c09ca4d5fd100c998a7e51bcComments.2017-10-02T07:46:10ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/cbaeea360f7a625a8cac0133ce5bb7001c8ef4ceCan configure number of sync registers.2017-10-02T07:13:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/8f3d4b8f5714fe6323e1177179a89af5e323c58aReady to have vme_lword FF in IOBs.2017-10-02T07:00:25ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/18f12bb4a298353fa1e38614c4fffe7a718c49bcPut FF for VME_DATA_i in IOBs, improve MBLT rate2017-10-02T07:00:07ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/948160107cbebb01aba129d6c092c7451346294eAllow VME_ADDR FF to be put in IOBs.2017-09-29T13:52:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/010af55097513711eb1145b5e67da4a4f69d6ea1irq controller: makes use of registers more explicit.2017-09-29T12:10:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/74e4bdd33d4a4de0cfd5f0c200ddaced87ee28deHandle IACK cycles in vme_bus to avoid mux after FF.2017-09-29T09:49:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/8e5d875f7134e0fd6e536a0aa551810d196ce282vme_bus: latch DS and decode address in parallel. Add testcase.2017-09-29T07:10:39ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/affa1990198cc5a3ec33b592a5871f0cb5e10836Add performance numbers in specs.txt2017-09-28T15:31:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d681e2a34577abdf1610001ef6c0661869e2301eDoc improved.2017-09-28T11:33:22ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3d8797da9d728296e05ff06795f309f2b8b83ef6Initial specifications for core v2.2017-09-28T09:55:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c6b3a685fdef4601ef7e1619e304495d666b56ccSupport MBLT.2017-09-27T14:37:01ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/4c5c2f7a56fe202b97377af63ac7c27fefa8773bLatch VME_WRITE.2017-09-22T14:09:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/98894891d8c5077b7b2b55620fc88717e6ed5062Remove unused rtl files.2017-09-22T14:09:14ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/3a60c1ba9a0539a02cda13c1699a0dde398e8c35Rescind DTACK.2017-09-22T11:37:27ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/95591095dba167818dc19b3d014e91565ad19f54Don't store unused bits of ADER.2017-09-22T11:36:58ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/e068a43f55bb825953f7bdd48745529aa7b35740top_tb: add new scenario2017-09-22T09:50:01ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/6ed6be9322b3969a01b04077b9883608bed8af33vme_bus: renaming.2017-09-22T09:49:43ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f6f0a7f05459ec0ceb943ced6796e4585d5046c0adjust xvme64x wrapper.2017-09-22T08:54:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0d53219412280b2a37383796ad4de9c7c0619233core: remove support of rty, simplify WB interface.2017-09-22T08:43:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0a8266698a3097eb253ae7874e5e166c3809fc28vme_bus: add comments, simplify berr generation.2017-09-21T14:45:30ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/56ee00aca29ee2871d912fbb2a94350e9bdde89dAdjust AMCAP bits (remove unsupported modes).2017-09-21T12:33:38ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7e121be49014f5be6fd1f06679dc024a929b1189Renaming of signals, remove some intermediate signals.2017-09-21T11:28:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/c393707193cee8fcc8626d30d0f700fb60bb1e57Rewrite decoder to decouple it from main FSM.2017-09-20T15:41:35ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/dca5417b8603d9910ad32381ecbf8c2bad564005top_tb: add comments about possible tests.2017-09-20T13:32:09ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/28acc296d580c61806143774ed8e4ba95fcedf60Fix check of supported AM.2017-09-20T13:31:52ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d16833812b73510072bbb0f62ea45b3e6ac7f29fOnly support 32b data WB bus.2017-09-20T13:31:31ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/01b08feed204809c8771496394ab478e7e134613xvme64x_core component: remove unused generics.2017-09-20T09:32:36ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/16982f5faec3da70a8393d68fbc63666b0889bffvme64x_pack: use common value for WB data and addr size.2017-09-20T09:32:03ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/9197cf129f7c46f126c694a6bf3da6cd9e80d79ccr_csr: handle the reset bit as a pulse.2017-09-20T09:29:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/40557d7a10fd2c10ed92aaa2acbd189cd4cbae5ccr/csr: remove unimplemented ader to reduce number of registers.2017-09-18T15:23:31ZTristan Gingoldtristan.gingold@cern.ch