VME64x core:0b0209c1815aea6baf98873f6fceaa189472674a commits
https://ohwr.org/project/vme64x-core/commits/0b0209c1815aea6baf98873f6fceaa189472674a
2020-04-24T08:25:15Z
https://ohwr.org/project/vme64x-core/commit/0b0209c1815aea6baf98873f6fceaa189472674a
top_tb: add a test for 2eSST.
2020-04-24T08:25:15Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/9388296e96fdeaaa288f4cd968f218d640c8d099
vme: preliminary support of 2eSST.
2020-04-24T08:25:15Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/e02c9e0fda00fc13d2aea58945250fa4a744e44e
vme_bus: add setup time.
2020-04-24T08:25:15Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/ef7107449b8811d0470e24ea23140a12fe96e509
vme_bus: add asynchronous control of dtack.
2020-04-24T08:25:15Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/a9f189404c6b6857be40e70f2f2165de66cc7a21
vme_bus: add raw ds input.
2020-04-24T08:25:15Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/8a4cc17fa0bef6b6fbf7e96e01621ca8adbfd517
vme_bus: make dtack output explicitely latched.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/65121f5ae7ed5cc955d31af458ba8f10ddc1c4ae
simple_tb: add one transaction.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/d7c03c1bb348b86286ceb3a5b00dc2ec333b4d1e
vme_bus: precharge data.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/c4e8308e6464f8fe8f516f06749217265aaeee5f
vme_bus: improve direction driving.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/7323094228ca9d8efe648bf4d2749444d0fb0d12
vme_bus: cleanup
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/29b8b02be06384133e57ed2e9305a1b86a5f87a1
vme_bus: cleanup
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/60f29f5d7e68bade86003a18def64226c69ffc8b
vme_bus: simulation is OK.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/a006c8508d1b9a4bebcd04a450543290d9934ecf
top_tb: add debug code.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/c8c501f5c278a811146728f06e32b2b3c8f7d2f1
vme_bus: new prefetch.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/e9ae25eb05fe1fa132c546f9d68ed3fb3d0b3914
simple_tb: simulate propagation for dtack.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/2cdedc10f2e126e3fdfd3f5b53cde79eafa0316f
vme_bus: renaming.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/b547692835d7ef8f81c0bde8490326ce84554d8b
vme_bus: reformatting.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/a5b91e6528f810bd00168949ed97544d5f83fa98
Add vme_bus.vhd original modifications from Milos Vojinovic.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/350d15cc8aca72924bf47b22c2ddc6f3167b3012
Reference general-cores with a git module.
2020-04-24T08:25:14Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/9a4a5b11794d9fdac287fa5f1f9f28a318633f20
simple_tb: improve run_all.sh
2020-04-14T08:18:10Z
Tristan Gingold
tgingold@free.fr
https://ohwr.org/project/vme64x-core/commit/d9342f87ec5e5f495bf3683f326eb754d73eec01
simple_tb/Manifest.py: use git module for general-cores
2020-04-14T08:14:22Z
Tristan Gingold
tgingold@free.fr
https://ohwr.org/project/vme64x-core/commit/6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
Add a comment.
2019-11-14T16:23:51Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/7b94b276cee0e2f89f31d6e29627a909f8e3a7bf
Add vme16_tb testbench
2019-11-11T13:39:13Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/2736fdff60dac9a8ae6ce09c7c22eb0431ec6036
Add ghdl support for simple_tb.
2019-11-11T13:38:39Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/a994813b6b5923786c6d36e216f617d994ec15f4
vme64x_pkg: rename c_AM_A24_S to c_AM_A24
2019-11-11T13:38:10Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/b9f87fb9ecf3d249b70bf7dbef3c0d97b8137800
vme64x_core: add g_VME32 generic (true by default).
2019-11-11T13:37:20Z
Tristan Gingold
tristan.gingold@cern.ch
Add support for a D16 only (still with D8) core.
https://ohwr.org/project/vme64x-core/commit/84da9bdd4fa033f1daad34a70441fc642306d639
top_tb: add entity name after 'end' for the sake of hdlmake.
2019-11-11T08:37:42Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/366ca4dbe1777f5bc98341d2878070a6c6fa350f
simple_tb: adjust scenario 9.
2019-07-24T10:09:07Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/3dd0b23a73a52168370a6329ef71d842ccc16752
sim: cleanup in vme bfm.
2019-07-24T09:37:11Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/4d39f9dfc2c58a3eb1f52f6548c9d49bd9eeff7d
xvme64x_core: add g_WB_MODE generic to select between classic/pipelined.
2019-07-24T09:36:29Z
Tristan Gingold
tristan.gingold@cern.ch
https://ohwr.org/project/vme64x-core/commit/1204aeca29ec3c72b6fa615976f000c664c7d152
Update general-cores submodule URL for new OHWR
2019-04-02T05:12:25Z
Tom Levens
tom.levens@cern.ch
https://ohwr.org/project/vme64x-core/commit/78cac8713658de449dcccbce5a5d35131461fc34
Invert RTY assertion logic to make simulators happier
2018-11-29T16:22:38Z
Dimitris Lampridis
dimitris.lampridis@cern.ch
https://ohwr.org/project/vme64x-core/commit/e0f5eaadc5ad774cf5a66c273882b89b4e309f1a
Implement amnesia address if parity is wrong
2018-10-26T11:27:23Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/ae052e7624b06a9367d6efd7667f517563d75544
Add new generic to component declaration
2018-10-26T11:14:41Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/c3d44ce486824d295bc9938c4e70eb611d1a4133
Cleanup alignment of code
2018-10-26T09:35:33Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/45cb91f4f7cbd01421ea222e1540e6d913bb9100
Fix references to ANSI/VITA standards
2018-10-26T08:39:47Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/44f9345f6995d70a5440f2c5a99c2c3fc4eecdee
Add generic to disable CR/CSR
2018-10-25T23:00:22Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/a2ee4ac44503153b30767970d1ee64cc640880b4
Normalise case of generics and ports
2018-10-25T23:00:16Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/cd83b258e245575534483964969b7bb999b4a165
Propagate defaults to parameters on vme64x_core
2018-10-25T23:00:09Z
Tom Levens
tom.levens@cern.ch
Signed-off-by: <span data-trailer="Signed-off-by:" data-user="9305"><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch"><img alt="Tom Levens's avatar" src="https://ohwr.org/project/vme64x-core/uploads/-/system/user/avatar/9305/avatar.png?width=16" class="avatar s16 avatar-inline" title="Tom Levens"></a><a href="https://ohwr.org/tlevens" title="tom.levens@cern.ch">Tom Levens</a> <<a href="mailto:tom.levens@cern.ch" title="tom.levens@cern.ch">tom.levens@cern.ch</a>></span>
https://ohwr.org/project/vme64x-core/commit/0ae24a25ae24cc9f9830c502a7881795238b54c2
run_all.sh: strenghten.
2018-08-17T14:09:26Z
Tristan Gingold
tristan.gingold@cern.ch