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VME64x core
Commits
ffb421dd
Commit
ffb421dd
authored
Mar 06, 2020
by
Tristan Gingold
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top_tb: remap ram.
parent
9d43711f
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37 additions
and
35 deletions
+37
-35
top_tb.vhd
hdl/testbench/simple_tb/top_tb.vhd
+37
-35
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hdl/testbench/simple_tb/top_tb.vhd
View file @
ffb421dd
...
...
@@ -422,10 +422,9 @@ begin
end
process
;
-- WB slave: a simple sram
-- WBaddr VMEaddr
-- 0-0x3ff 0-0xfff sram
-- 0x2000 0x8000 counter
-- 0x2001 0x8004 BERR
-- 0-0xfff sram
-- 0x4000 counter
-- 0x4004 BERR
wb_p
:
process
(
clk_i
)
constant
sram_addr_wd
:
natural
:
=
10
;
type
sram_array
is
array
(
0
to
2
**
sram_addr_wd
-
1
)
...
...
@@ -463,11 +462,11 @@ begin
end
if
;
end
if
;
if
STB_o
=
'1'
then
if
STB_o
=
'1'
and
CYC_o
=
'1'
then
ACK_i
<=
'1'
;
idx
:
=
to_integer
(
unsigned
(
ADR_o
(
sram_addr_wd
-
1
downto
0
)));
if
ADR_o
(
13
)
=
'1'
then
case
ADR_o
(
15
downto
12
)
is
when
"0001"
=>
if
ADR_o
(
0
)
=
'0'
then
if
WE_o
=
'0'
then
-- Read counter
...
...
@@ -483,7 +482,8 @@ begin
ACK_i
<=
'0'
;
ERR_i
<=
'1'
;
end
if
;
else
when
"0000"
=>
idx
:
=
to_integer
(
unsigned
(
ADR_o
(
sram_addr_wd
-
1
downto
0
)));
if
WE_o
=
'0'
then
-- Read SRAM
DAT_i
<=
sram
(
idx
);
...
...
@@ -495,7 +495,9 @@ begin
end
if
;
end
loop
;
end
if
;
end
if
;
when
others
=>
DAT_i
<=
(
others
=>
'0'
);
end
case
;
end
if
;
end
if
;
end
if
;
...
...
@@ -1234,7 +1236,7 @@ begin
-- Set IRQ level
write8_conf
(
x"7_ff5b"
,
x"03"
);
write8
(
x"67_00_
8
0_03"
,
c_AM_A32
,
x"02"
);
write8
(
x"67_00_
4
0_03"
,
c_AM_A32
,
x"02"
);
wait
for
2
*
g_CLOCK_PERIOD
*
1
ns
;
assert
VME_IRQ_n_o
=
"1111011"
report
"IRQ incorrectly reported"
severity
error
;
...
...
@@ -1247,7 +1249,7 @@ begin
-- Set IRQ vector
write8_conf
(
x"7_ff5f"
,
x"a3"
);
write8
(
x"67_00_
8
0_03"
,
c_AM_A32
,
x"20"
);
write8
(
x"67_00_
4
0_03"
,
c_AM_A32
,
x"20"
);
assert
VME_IRQ_n_o
=
"1111111"
report
"IRQ not expected"
severity
error
;
wait
for
32
*
g_CLOCK_PERIOD
*
1
ns
;
...
...
@@ -1333,7 +1335,7 @@ begin
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
read32
(
x"00_20_
8
0_04"
,
c_AM_A24
,
d32
);
read32
(
x"00_20_
4
0_04"
,
c_AM_A24
,
d32
);
assert
d32
=
(
31
downto
0
=>
'X'
)
report
"incorrect read 32"
severity
error
;
...
...
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