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VME64x core
Commit ffb421dd authored by Tristan Gingold's avatar Tristan Gingold
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top_tb: remap ram.

parent 9d43711f
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Showing with 37 additions and 35 deletions
hdl/testbench/simple_tb/top_tb.vhd
View file @ ffb421dd
...@@ -422,10 +422,9 @@ begin ...@@ -422,10 +422,9 @@ begin
end process; end process;
-- WB slave: a simple sram -- WB slave: a simple sram
-- WBaddr VMEaddr -- 0-0xfff sram
-- 0-0x3ff 0-0xfff sram -- 0x4000 counter
-- 0x2000 0x8000 counter -- 0x4004 BERR
-- 0x2001 0x8004 BERR
wb_p : process (clk_i) wb_p : process (clk_i)
constant sram_addr_wd : natural := 10; constant sram_addr_wd : natural := 10;
type sram_array is array (0 to 2**sram_addr_wd - 1) type sram_array is array (0 to 2**sram_addr_wd - 1)
...@@ -463,39 +462,42 @@ begin ...@@ -463,39 +462,42 @@ begin
end if; end if;
end if; end if;
if STB_o = '1' then if STB_o = '1' and CYC_o = '1' then
ACK_i <= '1'; ACK_i <= '1';
idx := to_integer (unsigned (ADR_o (sram_addr_wd - 1 downto 0)));
if ADR_o (13) = '1' then case ADR_o(15 downto 12) is
if ADR_o (0) = '0' then when "0001" =>
if ADR_o (0) = '0' then
if WE_o = '0' then
-- Read counter
DAT_i <= std_logic_vector (to_unsigned (int_cnt, 32));
else
-- Write counter
if SEL_o (0) = '1' then
int_cnt := to_integer(unsigned(DAT_o(7 downto 0)));
end if;
end if;
else
-- BERR
ACK_i <= '0';
ERR_i <= '1';
end if;
when "0000" =>
idx := to_integer (unsigned (ADR_o (sram_addr_wd - 1 downto 0)));
if WE_o = '0' then if WE_o = '0' then
-- Read counter -- Read SRAM
DAT_i <= std_logic_vector (to_unsigned (int_cnt, 32)); DAT_i <= sram (idx);
else else
-- Write counter -- Write SRAM
if SEL_o (0) = '1' then for i in 3 downto 0 loop
int_cnt := to_integer(unsigned(DAT_o(7 downto 0))); if SEL_o(i) = '1' then
end if; sram(idx)(8*i + 7 downto 8*i) := DAT_o (8*i + 7 downto 8*i);
end if;
end loop;
end if; end if;
else when others =>
-- BERR DAT_i <= (others => '0');
ACK_i <= '0'; end case;
ERR_i <= '1';
end if;
else
if WE_o = '0' then
-- Read SRAM
DAT_i <= sram (idx);
else
-- Write SRAM
for i in 3 downto 0 loop
if SEL_o(i) = '1' then
sram(idx)(8*i + 7 downto 8*i) := DAT_o (8*i + 7 downto 8*i);
end if;
end loop;
end if;
end if;
end if; end if;
end if; end if;
end if; end if;
...@@ -1234,7 +1236,7 @@ begin ...@@ -1234,7 +1236,7 @@ begin
-- Set IRQ level -- Set IRQ level
write8_conf (x"7_ff5b", x"03"); write8_conf (x"7_ff5b", x"03");
write8 (x"67_00_80_03", c_AM_A32, x"02"); write8 (x"67_00_40_03", c_AM_A32, x"02");
wait for 2 * g_CLOCK_PERIOD * 1 ns; wait for 2 * g_CLOCK_PERIOD * 1 ns;
assert VME_IRQ_n_o = "1111011" report "IRQ incorrectly reported" assert VME_IRQ_n_o = "1111011" report "IRQ incorrectly reported"
severity error; severity error;
...@@ -1247,7 +1249,7 @@ begin ...@@ -1247,7 +1249,7 @@ begin
-- Set IRQ vector -- Set IRQ vector
write8_conf (x"7_ff5f", x"a3"); write8_conf (x"7_ff5f", x"a3");
write8 (x"67_00_80_03", c_AM_A32, x"20"); write8 (x"67_00_40_03", c_AM_A32, x"20");
assert VME_IRQ_n_o = "1111111" report "IRQ not expected" assert VME_IRQ_n_o = "1111111" report "IRQ not expected"
severity error; severity error;
wait for 32 * g_CLOCK_PERIOD * 1 ns; wait for 32 * g_CLOCK_PERIOD * 1 ns;
...@@ -1333,7 +1335,7 @@ begin ...@@ -1333,7 +1335,7 @@ begin
-- Enable card -- Enable card
write8_conf (x"7_fffb", b"0001_0000"); write8_conf (x"7_fffb", b"0001_0000");
read32 (x"00_20_80_04", c_AM_A24, d32); read32 (x"00_20_40_04", c_AM_A24, d32);
assert d32 = (31 downto 0 => 'X') assert d32 = (31 downto 0 => 'X')
report "incorrect read 32" severity error; report "incorrect read 32" severity error;
......
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